Low latency interconnect bus protocol
A method for enabling a low latency medium access control for an interconnect bus protocol over a wireless medium is provided. The method comprises constructing a wireless medium access control (WMAC) frame, wherein the WMAC frame includes a plurality of medium access control service data units (MSDUs) being aggregated according to their transmission order, the MSDUs include transaction layer packets generated by a component of the interconnect bus, wherein transmission of the WMAC frame over the wireless medium provides any one of an implied acknowledgment (ACK) mechanism and a block ACK mechanism.
1. A method for enabling a medium access control for an interconnect bus over a wireless medium, comprising:
constructing a wireless medium access control (WMAC) frame, wherein the WMAC frame includes a plurality of medium access control service data units (MSDUs) being aggregated according to their transmission order, the MSDUs include transaction layer packets generated by a component of the interconnect bus;
transmitting the WMAC frame over the wireless medium wherein transmission of the WMAC frame provides an implied acknowledgment (ACK) mechanism or a block ACK mechanism, wherein the implied ACK mechanism is implemented by including, in the WMAC frame, a sequence number of a most-recent consecutive MSDU received, and wherein the block ACK mechanism is implemented by including, in the WMAC frame, a sequence number of a most-recent and non-consecutive acknowledged MSDU.
2. The method of claim 1 ,further comprising encapsulating the WMAC frame in a wireless physical (WPHY) frame, wherein the transmitting comprises transmitting the wireless physical (WPHY) frame.
3. The method of claim 1 , wherein the WMAC frame further comprises:
a header field constructed to maintain at least an indication of a buffer size of a receiver for enabling a flow control between a transmitter and the receiver; and
an error correction field including an error detection code computed based on a data portion of the WMAC frame and the header field.
4. The method of claim 1 , wherein the WMAC frame further comprises: a data portion constructed to maintain the aggregation of the plurality of MSDUs.
5. The method of claim 1 , wherein each MSDU comprises:
a sub-header constructed to maintain at least a length field; and
a payload constructed to maintain a data packet, an idle packet, or a block ACK.
6. The method of claim 1 , wherein the interconnect bus is a wireless peripheral component interconnect (PCI) express bus.
7. The method of claim 6 , wherein the PCI express bus comprises at least one of a switch, an endpoint, or a coordinator.
8. A non-transient computer readable medium for enabling a medium access control for an interconnect bus over a wireless medium having instructions stored thereon for:
constructing a wireless medium access control (WMAC) frame, wherein the WMAC frame includes a plurality of medium access control service data units (MSDUS) being aggregated according to their transmission order, the MSDUs include transaction layer packets generated by a component of the interconnect bus; and
transmitting the WMAC frame over the wireless medium, wherein transmission of the WMAC frame provides an implied acknowledgment (ACK) mechanism or a block ACK mechanism, wherein the implied ACK mechanism is implemented by including, in the WMAC frame, a sequence number of a most-recent consecutive MSDU received, and wherein the block ACK mechanism is implemented by including, in the WMAC frame, a sequence number of a most-recent and non-consecutive acknowledged MSDU.
9. An apparatus for enabling a medium access control for an interconnect bus over a wireless medium, comprising:
at least one processor configured to construct a wireless medium access control (WMAC) frame, wherein the WMAC frame includes a plurality of medium access control service data units (MSDUs) being aggregated according to their transmission order, the MSDUs include transaction layer packets generated by a component of the interconnect bus; and
a transmitter configured to transmite the WMAC frame over the wireless medium wherein transmission of the WMAC frame provides an implied acknowledgment (ACK) mechanism or a block ACK mechanism, wherin the implied ACK mechanism is implemented by including, in the WMAC frame, a sequence number of a most-recent consecutive MSDU received, and wherein the block ACK mechanism is implemented by including, in the WMAC frame, a sequence number of a most-recent and non-consecutive acknowledged MSDU.
10. The apparatus of claim 9 , wherein the interconnect bus is a wireless peripheral component interconnect (PCI) express bus.
11. The apparatus of claim 10 , wherein the PCI express bus comprises at least one of a switch, an endpoint, or a coordinator.
12. The apparatus of claim 9 , wherein the transmitted WMAC frame is encapsulated in a wireless physical (WPHY) frame.
13. The apparatus of claim 9 , wherein the WMAC frame further comprises:
a header field constructed to maintain at least an indication of a buffer size of a receiver for enabling a flow control between a transmitter and the receiver; and
an error correction field including an error detection code computed based on a data portion of the WMAC frame and the header field.
14. The apparatus of claim 9 , wherein the WMAC frame further comprises a data portion constructed to maintain the aggregation of the plurality of MSDUs.
15. The apparatus of claim 9 , wherein each MSDU comprises a sub-header constructed to maintain at least a length field and a payload constructed to maintain a data packet, an idle packet, or a block ACK.