IP Library Granted Patent US 9,674,538
Granted Patent B2
US 9,674,538 · App. 13/858,852 · Granted Jun 6, 2017

Methods for reconstructing an encoded video at a bit-depth lower than at which it was encoded

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,674,538
App. No.
13/858,852
Granted
Jun 6, 2017
Kind
B2
Abstract

Methods are provided for reconstructing d-bit samples from coefficients, in an encoded video bit-stream, that had been encoded based on source samples having a bit-depth D, where D>d. A residual process, including inverse-quantization and inverse-transformation processes, is applied to the coefficients to compute (D+1)-bit residual samples. Then a prediction process, including (i) rounding and/or truncating intermediate samples and (ii) subsequently clipping intermediate samples, is applied to the residual samples to compute d-bit reconstructed samples.

Claims (40)

1. A method of generating d-bit output samples from coefficients, in an encoded video bit-stream, encoded based on source samples having a bit-depth D, greater than d, the method comprising:

applying, to the coefficients, a residual process, the residual process including inverse-quantization and inverse-transformation processes, to compute (D+1)-bit residual samples; and

applying, to the (D+1)-bit residual samples, a prediction process, the prediction process including:

generating, at a d-bit prediction operation, d-bit prediction samples;

padding the d-bit prediction samples to generate D-bit prediction samples;

adding, at an addition operation, the D-bit prediction samples to the (D+1)-bit residual samples, thereby producing (D+2)-bit first intermediate samples;

rounding and truncating the (D+2)-bit first intermediate samples, thereby producing (d+2)-bit second intermediate samples, the rounding and truncating including:

a rounding operation; and

a right-shift operation subsequent to the rounding operation;

clipping the (d+2)-bit second intermediate samples, thereby producing d-bit reference samples for subsequent d-bit prediction operations; and

filtering, at an in-loop filtering operation, the d-bit reference samples, thereby generating the d-bit output samples.

2. The method of claim 1 , wherein the prediction process comprises:

determining that the bit-stream contains an indication that a sample-adaptive offset (SAO) is to be applied to a D-bit output from a distinct in-loop filtering operation in a distinct operational mode;

responsive to the determining, applying, instead, an SAO configured for the d-bit output samples.

3. The method of claim 2 , wherein applying the SAO comprises performing lookups in a table configured for use with the d-bit output samples from the in-loop filtering operation.

4. The method of claim 1 , wherein the rounding operation comprises one of: (a) rounding toward zero, (b) rounding toward negative infinity, (c) rounding toward positive infinity, (d) rounding half values toward zero, (e) rounding half values toward negative infinity, (f) rounding half values toward positive infinity, (g) rounding half values toward the nearest even value, (h) rounding half values toward the nearest odd value, (i) stochastic rounding, (j) spatial dithering, and (k) spatial dithering in combination with any one of (a) through (h).

5. A computing device comprising:

one or more processors; and

a memory containing processor-executable instructions that, when executed by the one or more processors, cause the device to:

apply a residual process to the coefficients, the residual process including inverse-quantization and inverse-transformation processes, to compute (D+1)-bit residual samples; and

apply a prediction process to the (D+1)-bit residual samples, the prediction process including:

generating, at a d-bit prediction operation, d-bit prediction samples;

padding the d-bit prediction samples to generate D-bit prediction samples;

adding, at an addition operation, the D-bit prediction samples to the (D+1)-bit residual samples, thereby producing (D+2)-bit first intermediate samples;

rounding and truncating the (D+2)-bit first intermediate samples, thereby producing (d+2)-bit second intermediate samples, the rounding and truncating including:

a rounding operation;

a right-shift operation subsequent to the rounding operation;

clipping the (d+2)-bit second intermediate samples, thereby producing d-bit reference samples for subsequent d-bit prediction operations; and

filtering, at an in-loop filtering operation, the d-bit reference samples, thereby generating output d-bit samples.

6. A non-transitory, processor-readable storage medium storing processor-executable instructions that, when executed by one or more processors of a computing device, cause the device to:

apply a residual process to the coefficients, the residual process including inverse-quantization and inverse-transformation processes, to compute (D+1)-bit residual samples; and

apply a prediction process to the (D+1)-bit residual samples, the prediction process including:

generating, at a d-bit prediction operation, d-bit prediction samples;

padding the d-bit prediction samples to generate D-bit prediction samples;

adding, at an addition operation, the D-bit prediction samples to the residual samples, thereby producing (D+2)-bit first intermediate samples;

rounding and truncating the (D+2)-bit first intermediate samples, thereby producing (d+2)-bit second intermediate samples, the rounding and truncating including:

a rounding operation;

a right-shift operation subsequent to the rounding operation;

clipping the (d+2)-bit second intermediate samples, thereby producing d-bit reference samples for subsequent d-bit prediction operations; and

filtering, at an in-loop filtering operation, the d-bit reference samples, thereby generating d-bit output samples.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE ADDED PATENT NUMBER TO REMOVE PATENT NO. 8,873,407 AT PREVIOUSLY RECORDED ON REEL 64066 FRAME 1. ASSIGNOR(S) HEREBY CONFIRMS THE NUNC PRO TUNC ASSIGNMENT EFFECTIVE DATE MARCH 20, 2023. Recorded Feb 2, 2026
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 074921/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE COVER SHEET AT PAGE 50 TO REMOVE 12817157 PREVIOUSLY RECORDED ON REEL 063471 FRAME 0474. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: BLACKBERRY LIMITED
To: OT PATENT ESCROW, LLC
Reel/Frame 064806/0669 →
CORRECTIVE ASSIGNMENT TO CORRECT 12817157 APPLICATION NUMBER PREVIOUSLY RECORDED AT REEL: 064015 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: OT PATENT ESCROW, LLC
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064807/0001 →
NUNC PRO TUNC ASSIGNMENT Recorded Jun 19, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064066/0001 →
NUNC PRO TUNC ASSIGNMENT Recorded Jun 16, 2023
From: OT PATENT ESCROW, LLC
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064015/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2023
From: BLACKBERRY LIMITED
To: OT PATENT ESCROW, LLC
Reel/Frame 063471/0474 →
CHANGE OF NAME Recorded Nov 5, 2014
From: RESEARCH IN MOTION LIMITED
To: BLACKBERRY LIMITED
Reel/Frame 034176/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2013
From: FLYNN, DAVID
To: RESEARCH IN MOTION LIMITED
Reel/Frame 031237/0952 →