IP Library Granted Patent US 9,230,950
Granted Patent B2
US 9,230,950 · App. 13/859,418 · Granted Jan 5, 2016

Method for producing an electronic device by assembling semi-conducting blocks and corresponding device

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Quick Facts
Patent No.
US 9,230,950
App. No.
13/859,418
Granted
Jan 5, 2016
Kind
B2
Abstract

At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.

Claims (39)

1. An electronic device comprising:

a substrate; and

a plurality of transistors in said substrate, each transistor comprising

an isolating region,

a drain block,

a source block,

a channel block between said drain and source blocks, and

a gate block being laterally spaced apart from and laterally outside of said drain, channel, and source blocks and being capacitively coupled by a part of the isolating region to said drain, channel, and source blocks,

said gate, drain, channel, and source blocks each having coplanar lowermost planar surfaces and coplanar uppermost planar surfaces,

at least two of the drain, channel, and source blocks having different semiconductor properties and being in mutual contact by one of their sides, the different semiconductor properties comprising at least one of different conductivity types or different dopant concentrations.

2. The electronic device according to claim 1 , wherein the gate, drain, and source blocks comprise respective electrical contact tap zones.

3. The electronic device according to claim 1 , wherein at least some of the blocks comprise a monocrystalline semiconductor structure.

4. The electronic device according to claim 1 , wherein at least some of the blocks comprise a polycrystalline semiconductor structure.

5. The electronic device according to claim 1 , wherein at least one part the isolating region comprises a field oxide filled trench.

6. An electronic device comprising:

a substrate; and

a plurality of logic circuits in said substrate, each logic circuit comprising

an isolating region,

a first resistor block,

a second resistor block, and

a control block being laterally spaced apart from and laterally outside of said first and second resistor blocks and being capacitively coupled by a part of the isolating region to said first and second resistor blocks,

said control, and first and second resistor blocks each having coplanar lowermost planar surfaces and coplanar uppermost planar surfaces,

at least two of the control, and first and second resistor blocks having different semiconductor properties and being in mutual contact by one of their sides, the different semiconductor properties comprising at least one of different conductivity types or different dopant concentrations.

7. The electronic device according to claim 6 , wherein at least some of the blocks comprise a monocrystalline semiconductor structure.

8. The electronic device according to claim 6 , wherein at least some of the blocks comprise a polycrystalline semiconductor structure.

9. The electronic device according to claim 6 , wherein at least one part the isolating region comprises a field oxide filled trench.

10. An electronic device comprising:

a substrate; and

a plurality of inverters in said substrate, each inverter comprising

an isolating region,

a drain block,

a source block,

a channel block between said drain and source blocks, and

a gate block being laterally spaced apart from and laterally outside of said drain, channel, and source blocks and being capacitively coupled by a part of the isolating region to said drain, channel, and source blocks,

said gate, drain, channel, and source blocks each having coplanar lowermost planar surfaces and coplanar uppermost planar surfaces,

at least two of the drain, channel, and source blocks having different semiconductor properties and being in mutual contact by one of their sides, the different semiconductor properties comprising at least one of different conductivity types or different dopant concentrations.

11. The electronic device according to claim 10 , wherein at least some of the blocks comprise a monocrystalline semiconductor structure.

12. The electronic device according to claim 10 , wherein at least some of the blocks comprise a polycrystalline semiconductor structure.

13. The electronic device according to claim 10 , wherein at least one part the isolating region comprises a field oxide filled trench.

Assignments (2)
CHANGE OF NAME Recorded Jul 1, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 068104/0472 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2013
From: GALY, PHILIPPE; JIMENEZ, JEAN
To: STMICROELECTRONICS SA
Reel/Frame 030186/0378 →