Fully integrated differential LC PLL with switched capacitor loop filter

1. A circuit comprising:

a loop filter, wherein the filter comprises an active integrator configured to generate one or more tuning signals; and

a voltage-controlled oscillator (VCO) coupled to the loop filter and configured to generate a feedback signal based on the one or more tuning signals,

wherein generating the one or more tuning signals is based on the feedback signal,

wherein the loop filter is implemented on an integrated chip, and

wherein the loop filter does not comprise a capacitor that is external to the integrated chip and used to generate the tuning signals.

2. A circuit comprising:

a loop filter, wherein the filter comprises an active integrator configured to generate one or more tuning signals; and

a voltage-controlled oscillator (VCO) coupled to the loop filter and configured to generate a feedback signal based on the one or more tuning signals,

wherein generating the one or more tuning signals is based on the feedback signal,

wherein the active integrator is a differential integrator comprising a differential pair of operational amplifiers (OAs), and

wherein the differential pair of OAs are both configured to receive the feedback signal.

3. A circuit comprising:

a loop filter, wherein the filter comprises an active integrator configured to generate one or more tuning signals; and

a voltage-controlled oscillator (VCO) coupled to the loop filter and configured to generate a feedback signal based on the one or more tuning signals,

wherein generating the one or more tuning signals is based on the feedback signal, and

wherein the active integrator comprises one or more operational amplifiers (OAs) each configured to receive the feedback signal.

4. The circuit of claim 3 , wherein the active integrator further comprises a number of capacitors coupled to the one or more OAs, wherein none of the capacitors has a value greater than 1 picofarad (pF), and wherein the active integrator does not contain any external capacitor.

5. The circuit of claim 3 , wherein the loop filter further comprises a sample and hold (SH) circuit coupled to the active integrator and configured to:

receive a reference clock signal with a period comprising a first duration and a second duration;

close at least one switch of the SH circuit at the beginning of the first duration;

sample the one or more tuning signals during the first duration by charging at least one capacitor of the SH circuit;

open the at least one switch of the SH circuit at the beginning of the second duration; and

hold the charge on the at least one capacitor during the second duration.

6. The circuit of claim 5 , wherein the loop filter further comprises at least one additional resistor-capacitor (RC) circuit coupled to the SH circuit and configured to:

filter the one or more tuning signals to generate one or more filtered tuning signals; and

feed the filtered tuning signals to the VCO.

7. The circuit of claim 3 , wherein the loop filter further comprises a differentiator coupled to the differential integrator, wherein the differentiator is configured to:

receive two input signals;

generate two output signals by differentiating the two input signals; and

feed the two output signals to the differential integrator via two nodes,

wherein generation of the one or more tuning signals is based on the two output signals.

8. The circuit of claim 7 , wherein the differentiator comprises a plurality of switches and one or more capacitors, wherein any of the one or more capacitors is coupled in series to at least one of the plurality of switches, and wherein the differentiator contains no active component.

9. The circuit of claim 7 , further comprising:

a charge pump (CP) comprising an integral path and a proportional path, coupled to the differentiator, coupled to the active integrator, and configured to:

generate the two input signals and two additional signals based on the feedback signal;

feed the two input signals to the differentiator using the proportional path; and

feed the two additional signals to the active integrator directly using the integral path and via the two nodes, wherein generation of the one or more tuning signals is further based on the two additional signals.

10. The circuit of claim 9 , wherein all center taps of the CP are coupled to an input of at least one of the OAs.

11. The circuit of claim 3 , wherein the VCO comprises one or more linear elements and one or more nonlinear elements, and wherein values of the linear and nonlinear elements are configured such that tuning characteristics of the VCO are linearized.

12. The circuit of claim 11 , wherein the linear and nonlinear elements are capacitors and varactors respectively, and wherein configuration of the linear and nonlinear elements uses a weighted combination of capacitances of the capacitors and varactors.

13. A method implemented by a voltage-controlled oscillator (VCO) comprising:

receiving a tuning voltage; and

generating an oscillating signal whose frequency is based on the tuning voltage,

wherein a relationship between the tuning voltage and the frequency of the oscillating signal is characterizable via frequency versus voltage curves, and

wherein spacings between frequency versus voltage curves of the VCO are linear and a slope of the frequency versus voltage curves is substantially constant.

14. The method of claim 13 , wherein the VCO comprises a number of linear elements and a number of nonlinear elements, and wherein a total capacitance of the VCO is a weighted combination of capacitances of the linear elements and capacitances of the nonlinear elements.

15. The method of claim 14 , wherein each of the linear and nonlinear elements corresponds to a weight in the weighted combination, and wherein the weight of each element is determined based on a VCO band number.

16. A phase lock loop (PLL) comprising:

an active low pass filter configured to generate one or more tuning signals; and

a voltage-controlled oscillator (VCO) coupled to the active low pass filter and configured to:

generate a feedback signal based on the one or more tuning signals; and

feed the feedback signal to the active low pass filter.

17. The PLL of claim 16 , wherein the active low pass filter comprises a pair of operational amplifiers (OAs) coupled to each other in a differential configuration and configured to receive the feedback signal.

18. The PLL of claim 17 , wherein the active low pass filter further comprises a sample and hold (SH) circuit coupled to the OAs and configured to:

receive a reference clock signal with a period comprising a first duration and a second duration;

sample the one or more tuning signals during the first duration by charging at least one capacitor of the SH circuit; and

hold the charge on the at least one capacitor during the second duration.

19. The PLL of claim 17 , wherein the loop filter further comprises at least one additional resistor-capacitor (RC) circuit coupled to the active low pass filter and configured to:

filter the one or more tuning signals to generate one or more filtered tuning signals; and

feed the filtered tuning signals to the VCO.

20. The PLL of claim 17 , wherein the active low pass filter further comprises a differential differentiator coupled to the pair of OAs, wherein the differential differentiator is configured to:

receive two input signals;

generate two output signals by differentiating the two input signals; and

feed the two output signals to the differential integrator via two nodes,

wherein generation of the one or more tuning signals is based on the two output signals.