Phase shift circuit and power factor correction circuit including the same

1. A phase shift circuit, comprising:

a ramp generation unit charging or discharging a capacitor connected to a switch device to generate a ramp signal;

a reference signal generation unit generating a predetermined reference signal from the ramp signal; and

a comparison unit comparing the ramp signal with the reference signal to generate a clock signal,

wherein at least one of the reference signal generation unit and the comparison unit changes a negative or positive value of offset components included in the reference signal or the ramp signal within every operating period of the switch device.

2. The phase shift circuit of claim 1 , wherein the reference signal generation unit includes:

a reference level detection unit detecting half of a peak value of the ramp signal; and

a sample and hold circuit sampling the reference level and transferring the sampled reference level to a non-inverting terminal of the comparison unit.

3. The phase shift circuit of claim 2 , wherein at least one of the reference level detection unit and the comparison unit changes a negative or positive value of the offset components included in the reference signal or the ramp signal within every operating period of the switch device.

4. The phase shift circuit of claim 1 , wherein the operating period of the switch device is determined by current flowing in an inductor of a power factor correction circuit operated by a clock signal output by the comparison unit.

5. The phase shift circuit of claim 4 , wherein the current flowing in the inductor is detected by a zero point crossing method.

6. The phase shift circuit of claim 1 , wherein the comparison unit generates the clock signal so that an average value of a turn-on time of the clock signal within one period corresponds to a half value of one period of the clock signal.

7. A power factor correction circuit, comprising:

a detection circuit unit detecting current flowing in inductors included in a main circuit and a sub circuit, respectively, to generate a voltage pulse signal;

a control unit operating a switch device during every period of the voltage pulse signal to charge and discharge a capacitor and generate a control signal; and

a driving circuit unit determining operations of switches included in the main circuit and the sub circuit, respectively, based on the control signal and the voltage pulse signal,

wherein the control unit charges and discharges the capacitor to generate a ramp signal and compares a reference signal determined from the ramp signal with the ramp signal to generate a clock signal, and

a negative or positive value of offset components included in the reference signal or the ramp signal is changed during every operating period of the switch device.

8. The power factor correction circuit of claim 7 , wherein the control unit includes:

a phase shift circuit outputting the clock signal; and

a control signal generation circuit generating a control voltage based on the voltage pulse signal and the clock signal.

9. The power factor correction circuit of claim 8 , wherein the control signal generation circuit determines a level of the control signal from a phase difference between the clock signal and the voltage pulse signal.

10. The power factor correction circuit of claim 9 , wherein the control signal generation circuit increases the level of the control signal when a phase of the voltage pulse signal generated from the current flowing in the inductor included in the sub circuit is earlier than that of the clock signal, and

reduces the level of the control signal when the phase of the voltage pulse signal generated from the current flowing in the inductor included in the sub circuit is later than that of the clock signal.

11. The power factor correction circuit of claim 8 , wherein the detection circuit unit generates the voltage pulse signal using a zero point crossing method.

12. The power factor correction circuit of claim 7 , wherein the driving circuit unit includes:

a ramp generation unit generating a first ramp voltage having a fixed slope and a second ramp voltage having a variable slope from the control signal;

a comparison circuit unit comparing the first ramp voltage and the second ramp voltage with a predetermined reference voltage; and

a flip-flop generating driving signals for switches included in the main circuit and the sub circuit, respectively, based on the output of the comparison circuit unit and the voltage pulse signal.

13. The power factor correction circuit of claim 12 , wherein the comparison circuit unit compares an output voltage of at least one of the main circuit and the sub circuit with a band gap reference (BGR) voltage to generate the reference voltage.