Circuit arrangement, a method for testing a supply voltage provided to a test circuit, and a method for repairing a voltage source

1. A circuit arrangement, comprising:

a memory comprising a memory cell array comprising a plurality of memory cells;

a voltage source configured to provide at least one supply voltage;

a test circuit integrated with the memory cell array and the voltage source, wherein the test circuit receives the supply voltage;

the test circuit comprising:

at least one test memory cell,

wherein the at least one test memory cell comprises a first test memory cell corresponding to a lower bound of the supply voltage and a second test memory cell corresponding to an upper bound of the supply voltage;

at least one failure detection circuit configured to detect a data retention failure in the at least one test memory cell;

wherein the at least one failure detection circuit comprises a first failure detection circuit configured to detect a data retention failure in the first test memory cell corresponding to the lower bound of the supply voltage and a second failure detection circuit configured to detect a data retention failure in the second test memory cell corresponding to the upper bound of the supply voltage.

2. The circuit arrangement of claim 1 , the test circuit further comprising:

a data retention stability tuning circuit configured to tune a data retention stability of the at least one test memory cell.

3. The circuit arrangement of claim 1 ,

wherein the voltage source is configured to provide a first supply voltage and a second supply voltage.

4. The circuit arrangement of claim 3 ,

the memory further comprising a memory peripheral circuit configured to provide access to the memory cell array;

the circuit arrangement further comprising:

a first switching structure coupled between the voltage source and the memory cell array and configured to provide the first supply voltage to the memory cell array;

a second switching structure coupled between the voltage source and the memory peripheral circuit and configured to provide the second supply voltage to the memory peripheral circuit.

5. The circuit arrangement of claim 1 ,

wherein the voltage source comprises a voltage regulator.

6. The circuit arrangement of claim 1 ,

the test circuit further comprising a data retention stability tuning circuit configured to tune the data retention stability of the at least one test memory cell;

wherein the data retention stability tuning circuit and the first test memory cell provide the data retention stability of the first test memory cell, and wherein the data retention stability tuning circuit and the second test memory cell provide the data retention stability of the second test memory cell different from the data retention stability of the first test memory cell.

7. The circuit arrangement of claim 1 ,

wherein the data retention stability tuning circuit and the first test memory cell provide a data retention stability of the first test memory cell at a first pre-defined supply voltage; and

wherein the data retention stability tuning circuit and the second test memory cell provide a data retention stability of the second test memory cell at a second pre-defined supply voltage different from the first pre-defined supply voltage.

8. The circuit arrangement of claim 1 ,

wherein the at least one test memory cell has a lower data retention stability than the plurality of memory cells of the memory cell array.

9. The circuit arrangement of claim 1 ,

wherein the plurality of memory cells comprises a volatile memory cell.

10. The circuit arrangement of claim 9 ,

wherein the random access memory cell comprises a static random access memory cell.

11. The circuit arrangement of claim 1 ,

wherein the test circuit comprises a control circuit configured to control a test of the voltage source.

12. The circuit arrangement of claim 11 ,

wherein the control circuit implements a finite state machine to control the test of the voltage source.

13. The circuit arrangement of claim 1 , further comprising:

a voltage source setting circuit configured to set the voltage source.

14. The circuit arrangement of claim 13 ,

wherein the voltage source setting circuit is configured to repeatedly set the voltage source based on a test result signal provided by the test circuit.

15. A circuit arrangement, comprising:

a memory comprising a memory cell array comprising a plurality of memory cells;

a voltage source configured to provide at least one supply voltage;

a test circuit comprising a first test memory cell and a second test memory cell integrated with the memory cell array and the voltage source, wherein the test circuit receives the supply voltage;

the test circuit configured to determine whether the first and the second test memory cells fulfill a pre-defined test criterion;

wherein the pre-defined test criterion is based on a first voltage level tested in the first test memory cell and a second voltage level tested in the second test memory cell different from the first voltage level; and

wherein the first voltage level comprises a lower bound of the supply voltage, and wherein the second voltage level comprises an upper bound of the supply voltage.

16. A method for testing a supply voltage provided to a test circuit, the method comprising:

storing data in the test circuit comprising a first test memory cell and a second test memory cell provided with a voltage different from the supply voltage;

providing the supply voltage to the test circuit storing the data;

determining whether the data is stored in the test circuit provided with the supply voltage; and

determining whether the supply voltage fulfills a pre-defined test criterion.

17. The method of claim 16 ,

wherein the pre-defined test criterion is based on a first voltage level and a second voltage level different from the first voltage level.