Granted Patent B2

US 8,775,853 · App. 13/863,946 · Granted Jul 8, 2014

Abstract

Claims (42)

1. A method for synchronizing two connection nodes, the method comprising:

setting a maximum synchronization detection time between a transmission node and a reception node;

determining that the transmission node and reception node are synchronized at an early detection time, wherein the early detection time is less than the maximum synchronization detection time;

correcting a clock data recovery circuit when the transmission node and the reception node are unsynchronized to perform a resynchronization process; and

performing the resynchronization process based on the corrected clock data recovery circuit to establish synchronization between the transmission node and the reception node before the maximum synchronization detection time is reached.

2. The method according to claim 1 , wherein the correcting includes resetting the clock data recovery circuit.

3. The method according to claim 2 , wherein the correcting includes repeating the resetting within the maximum synchronization detection time until the synchronization is established.

4. The method according to claim 1 , wherein the correcting includes increasing a response sensitivity of the clock data recovery circuit.

5. The method according to claim 4 , wherein the correcting includes repeating the increasing the response sensitivity within the maximum synchronization detection time until the synchronization is established.

6. The method according to claim 5 , further comprising:

decreasing the response sensitivity after the synchronization is established.

7. The method according to claim 6 , further comprising:

setting the response sensitivity of the clock data recovery circuit with an initial gain parameter, wherein:

the increasing the response sensitivity includes setting the response sensitivity of the clock data recovery circuit with a first gain parameter that is greater than the initial gain parameter; and

the decreasing the response sensitivity includes setting the response sensitivity of the clock data recovery circuit with a second gain parameter that is less than the initial gain parameter.

8. The method according to claim 1 , wherein the connection nodes operate at a first frequency and a second frequency, respectively, the method further comprising:

detecting a frequency difference between the connection nodes; and

correcting the clock data recovery circuit when the detected frequency difference exceeds a tolerance value within the maximum synchronization detection time.

9. The method according to claim 1 , further comprising:

performing a connection interruption process when the synchronization is lost after the synchronization is once established; and

changing a response sensitivity of the clock data recovery circuit at least including decreasing the response sensitivity of the clock data recovery circuit after the synchronization is established.

10. The method according to claim 1 , further comprising determining a connection failure between the transmission node and the reception node when the resynchronization process is not completed before the maximum synchronization detection time is reached.

11. A device, the device comprising:

a clock data recovery circuit configured to generate a synchronization clock from input data;

a synchronization detection circuit configured to determine that transmission node and a reception node are synchronized at an early detection time, wherein the early detection time is less than a maximum synchronization detection time and to generate a synchronization detection signal;

a timer circuit configured to set the maximum synchronization detection time and the early detection time;

a correction processor configured to correct the clock data recovery circuit based on the synchronization detection signal; and

a resynchronization processor configured to perform a resynchronization process based on the corrected clock data recovery circuit to establish synchronization between the transmission and reception nodes before the maximum synchronization detection time is reached.

12. The device according to claim 11 , further comprising:

a frequency difference detection unit configured to detect a frequency difference between the input data and the synchronization clock and to generate a frequency difference signal, wherein the correction processor is further configured to correct the clock data recovery circuit in accordance with the frequency difference signal and the maximum synchronization detection time.

13. The device according to claim 11 , further comprising:

a data string detection circuit configured to detects a state of a string of the input data and generates a data string detection signal;

a connection interruption processor configured to perform a connection interruption process in accordance with the data string detection signal; and

a response sensitivity changing unit configured to change the response sensitivity of the clock data recovery circuit at least including decreasing the response sensitivity of the clock data recovery circuit in accordance with the synchronization detection signal.

14. The device according to claim 11 , wherein the correction processor includes:

a microcomputer; and

a notification unit configured to notify the microcomputer of a retry notification signal when the synchronization is not established when the early detection time elapses,

wherein the microcomputer corrects the clock data recovery circuit in response to the retry notification signal.

15. The device according to claim 14 , wherein:

the correction processor further includes a register configured to store a response sensitivity set for the clock data recovery circuit; and

the microcomputer is configured to rewrite the register to increase the response sensitivity in response to the retry notification signal.

16. The device according to claim 14 , wherein the notification unit includes an interrupt processor configured to generate the retry notification signal as an interrupt signal provided to the microcomputer.

Assignments (10)