Signal processing circuit

1. A signal processing circuit, comprising:

a plurality of sequence control units each for performing sequence control based on data and an instruction; and

an arithmetic operation processing unit for performing arithmetic operation processing based on a request for an arithmetic operation from any of the sequence control units,

wherein the arithmetic operation processing unit includes:

a common arithmetic operation element shared between or among_the sequence control units; and

an arbitration circuit for, when the sequence control units simultaneously generate the arithmetic operation requests to use the common arithmetic operation element, selecting one of the sequence control units based on priority information about each of the sequence control units set prior to the simultaneous generation of the arithmetic operation requests, causing the common arithmetic operation element to execute the arithmetic operation requested from the selected sequence control unit, and returning a result of the arithmetic operation to the selected sequence control unit.

2. The signal processing circuit according to claim 1 ,

wherein the common arithmetic operation element shared between or among the sequence control units includes a plurality of the common arithmetic operation elements each for an arithmetic operation type in a first group, and

wherein, when the sequence control units simultaneously generate the arithmetic operation requests to use the common arithmetic operation elements each for the arithmetic operation type in the first group, the arbitration circuit selects the sequence control units based on the priority information about each of the sequence control units, causes the individually allocated common arithmetic operation elements each for the arithmetic operation type in the first group to execute the arithmetic operations requested from the selected sequence control units, and returns results of the arithmetic operations to the respective selected sequence control units.

3. The signal processing circuit according to claim 1 ,

wherein the sequence control units generate requests for arithmetic operations of a plurality of arithmetic operation types,

the signal processing circuit comprising the common arithmetic operation element for each of the arithmetic operation types on a one-to-one basis,

wherein, when the sequence control units simultaneously generate requests for arithmetic operations of the same arithmetic operation type, the arbitration circuit selects any one of the sequence control units based on the priority information about each of the sequence control units, causes the common arithmetic operation element corresponding to the arithmetic operation type to execute the arithmetic operation requested from the selected sequence control unit, and returns a result of the arithmetic operation to the selected sequence control unit.

4. The signal processing circuit according to claim 3 ,

wherein, when the sequence control units simultaneously generate the requests for the arithmetic operations of the same arithmetic operation type, as long as the arithmetic operation element corresponding to the arithmetic operation type is out of use, the arbitration circuit selects any one of the sequence control units based on the priority information about each of the sequence control units, causes the common arithmetic operation element corresponding to the arithmetic operation type to execute the arithmetic operation requested from the selected sequence control unit, and returns a result of the arithmetic operation to the selected sequence control unit.

5. The signal processing circuit according to claim 2 ,

wherein the arbitration circuit returns the results of the arithmetic operations obtained after an arithmetic operation processing time shown by delay information about the arithmetic operation type to the selected sequence control units.

6. The signal processing circuit according to claim 2 ,

wherein the arbitration circuit sets, after selecting the sequence control units, the common arithmetic operation elements corresponding to the arithmetic operation type to an in-use state and returns a response signal for reporting reception of the arithmetic operation request to each of the selected sequence control units.

7. The signal processing circuit according to claim 2 ,

wherein the arbitration circuit returns a completion signal for reporting completion of the arithmetic operation to each of the selected sequence control units after an arithmetic operation processing time shown by delay information.

8. The signal processing circuit according to claim 7 , further comprising:

a memory unit for holding a group of instructions to be executed for each of the sequence control units on a one-to-one basis,

wherein the sequence control unit receives the completion signal and then reads the next instruction from the corresponding memory unit.

9. The signal processing circuit according to claim 8 , further comprising:

a data memory unit which can be specified as a source or a destination from or to which a value applied to the arithmetic operation is to be input or output for each of the sequence control units on a one-to-one basis,

wherein the sequence control unit can order reading of the value from the data memory unit and writing of the value to the data memory unit in accordance with the instruction read from the instruction memory unit.