Memory system having high data transfer efficiency and host controller

1. A host system comprising: a CPU; a host controller; a system memory configured to be accessed by the CPU and the host controller, the system memory configured to store data, a first descriptor, and a plurality of third and fourth descriptors; and a memory device which is connected to the host controller through an interface, wherein the host controller includes: a register set which is configured to control a command which is issued to the memory device; and a direct memory access (DMA) unit which is configured to load the first, third, and fourth descriptors in the system memory, and is configured to transfer data between the system memory and the memory device according to the first, third, and fourth descriptors, said host controller is configured to load the first descriptor which includes a set of a plurality of pointers indicating the third descriptors, each of the third descriptors including information necessary to issue the command to the memory device, and information necessary for data transfer between the host controller and the memory device, each of the third descriptors is followed by each of the fourth descriptors, and each of the fourth descriptors including information necessary for data transfer between the host controller and the system memory, and the host controller is configured (1) to set contents of each of the third descriptors to the register set, and issues the command to the memory device, (2) to execute the DMA unit to transfer data between the system memory and the memory device via the host controller in accordance with contents of each of the third descriptors and each of the fourth descriptors, and (3) to repeat (1) and (2) for each third descriptor and fourth descriptor indicated by each pointer in the first descriptor, wherein the host controller is configured to generate an interrupt signal indicating all data transfer described in the first descriptor has been completed.

2. The host system according to claim 1 , wherein the CPU executes a host driver stored in the system memory, the host driver transfers the data between the host controller and the memory device, and generates the first, third and fourth descriptors in accordance with position of data on the system memory and the memory device, the first, third and fourth descriptors generated by the host driver are stored in the system memory, the host driver designates start of the DMA data transfer to the host controller, and processes interrupts generated by the host controller when the DMA data transfer is completed or when a data transfer is stopped by an error.

3. The host system according to claim 1 , wherein the host controller comprises: a system address controller configured to control an address of the system memory pointing to data and each of the first descriptor, the third descriptors, and the fourth descriptors; a command controller configured to set, to the register set of the host controller, contents of the third descriptors read from the system memory to issue the command to the memory device; and a data buffer configured to store data from the system memory and read the data stored from the system memory to write the data to the memory device, or to store data from the memory device and read the data stored from the memory device to write the data to the system memory.

4. The host system according to claim 1 , wherein each of the first descriptor, the third descriptors, and the fourth descriptors has attribute information containing information for identifying a type of descriptor, and information indicating size of the respective descriptor.

5. The host system according to claim 1 , wherein the third descriptors includes information necessary to set a command argument, a command number, a command operation mode, a block length and the number of blocks; wherein each of the fourth descriptors includes information indicating necessary to designate a system memory area; addresses and sizes of a plurality of data arranged in the system memory.

6. The host system according to claim 1 , wherein the data transfer between the host controller and the memory device is started by the command.

7. The host system according to claim 6 , wherein the memory device acquires information necessary for the data transfer between the host controller and the memory device from the command.