Method and apparatus for smoothing jitter generated by byte stuffing
View Patent ↗Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a PLL. The smoothing logic is configured to modify a phase error signal generated by a phase frequency detector into a distributed phase error signal that spread over multiple clock cycles. The distributed phase error signal is used to drive a DCO. The smoothing logic may comprise a ramping logic operable to generate a series of ramping values to substitute a phase difference in the phase error signal. The phase difference may correspond to a stuffing byte.
1. A method of jitter attenuation, said method comprising:
providing an input signal to a phase lock loop (PLL);
detecting a phase difference between said input signal and a feedback signal of said PLL and generating a first phase error signal; and
converting said first phase error signal to a second phase error signal comprising a smaller average gradient than said first phase error signal, wherein:
said converting said first phase error signal comprises generating a sequence of ramping values and adding each of said sequence of ramping values to said first phase error signal for a plurality of clock cycles; and an initial value of said sequence of ramping values is equal to an additive inverse of said phase difference.
2. The method of claim 1 , wherein said generating a sequence of ramping values comprises:
dividing said first phase difference by N to generate a step value, where N is a positive integer; and
during a respective clock cycle of said plurality of clock cycles, subtracting said step value from a preceding ramping value to generate a respective ramping value.
3. The method of claim 2 further comprising determining N based on an estimated occurrence frequency of detectable phase differences.
4. The method of claim 1 further comprising providing said second phase error signal to a loop filter coupled with a digital controlled oscillator (DCO), and generating an output signal of said PLL, wherein said output signal comprise less jitter than said input signal.
5. The method of claim 1 further comprising generating said input signal by removing pulses from a stream of pulses.
6. The method of claim 5 further comprising incorporating stuffing information while removing pulses from said stream of pulses, wherein said phase difference corresponds to a negative justification opportunity or a positive justification opportunity indicated by said stuffing information.
7. An integrated circuit for frequency synthesis, said integrated circuit comprising:
a phase locked loop (PLL) comprising a phase frequency detector configured to output a phase error signal based on comparison between an input signal and a feedback signal of said PLL; and
smoothing logic coupled to said phase frequency detector and configured to distribute a phase step in said phase error signal to a plurality of clock cycles, wherein: said smoothing logic comprises ramping logic configured to generate a plurality of ramping values during said plurality of clock cycles; said plurality of ramping values have amplitudes smaller than an amplitude of said phase step; said plurality of ramping values comprise an initial value that is equal to an additive inverse of said phase step; and said ramping logic comprises a first adder/subtractor configured to subtract a step value from a preceding ramping value during a respective clock cycle of said plurality of clock cycles and output a respective ramping value of said plurality of ramping values; and
a register to store said initial value.
8. The integrated circuit of claim 7 further comprising a second adder/subtractor coupled to said phase detector and said smoothing logic, said second adder/subtractor operable to:
add said plurality of ramping values to said phase error signal during said plurality of clock cycles; and
output a ramped phase error signal.
9. The integrated circuit of claim 8 , wherein said PLL further comprises a loop filter coupled to said second adder/subtractor and configured to receive said ramped phase error signal, and a digital controlled oscillator (DCO) coupled to said loop filter.
10. The integrated circuit of claim 8 , wherein said plurality of clock cycles comprise N consecutive clock cycles, wherein said step value is substantially equal to said initial value divided by said N.
11. The integrated circuit of claim 8 further comprising rate estimation logic configured to derive said N in accordance with an estimation on an occurrence frequency of phase steps in said phase error signal, wherein said rate estimation logic comprises a divider coupled with a window counter, and a stuffing/gap counter.
12. The integrated circuit of claim 8 , further comprising, a gapper coupled with said PLL, wherein said input signal comprises a gapped clock generated by said gapper wherein said gapped clock generated by said gapper is generated responsive to stuffing information.
13. The integrated circuit of claim 12 further comprising a stuffing processor coupled with said gapper, wherein said stuffing processor is operable to process stuffing information, wherein said input signal comprises a byte-stuffed clock, wherein said smoothing logic further comprises control logic coupled to said stuffing processor and operable to control an input to said second adder/subtractor in accordance with stuffing information.
14. The integrated circuit of claim 7 , further comprising, a gapper coupled with said PLL, wherein said input signal comprises a gapped clock generated by said gapper wherein said PLL further comprises: a first integer divider coupled between said gapper and said phase frequency detector; a second integer divider coupled between a DCO and an output of said PLL, and a third integer divider disposed in the feedback loop of said PLL.
15. A method of frequency synthesis, said method comprising:
providing a gapped signal to a phase locked loop (PLL);
detecting a phase difference between said gapped signal with a feedback signal of said PLL to generate a first phase error signal;
converting said first phase error signal to a second phase error signal having a smaller average gradient than said first phase error signal; and
generating an output signal of said PLL responsive to said second phase error signal, said output signal having said output frequency;
removing pulses from an input signal having an input frequency in accordance with a predetermined ratio of said input frequency to an output frequency; and
incorporating stuffing information when removing pulses from said input signal, wherein said phase difference corresponds to a phase shift caused by said stuffing information.
16. The method of claim 15 further comprising multiplying said gapped signal with a rational number.
17. The method of claim 15 , wherein converting said first phase error signal comprises ramping said phase difference to a plurality of clock cycles and before a next phase difference is detected.