System and method for storing data in a virtualized memory system with destructive reads
View Patent ↗A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. To improve memory performance destructive read operations are used when reading data but the data is written back into the physical memory in a later cycle.
1. A method of handling memory access requests in a digital memory system, said method comprising:
receiving a first memory access request, said first memory access request identifying a first virtualized memory address in a virtualized memory address space;
translating said first virtualized memory address into a first physical memory address using a virtualized translation table wherein said physical memory address space is larger than said virtualized memory address space, said translating comprising
accessing said virtualized translation table using a first subset of said first virtualized memory address as an index to read out a set of entries from said virtualized translation table,
storing said set of entries read from said virtualized translation table into a temporary register when said first memory access request is a read request,
accessing said temporary register if a write operation to said first virtualized memory address is received a few clock cycles after said first memory access request to aid in handling said write operation
identifying a first memory bank from a set of N memory banks that currently represents said first virtualized memory address using set of entries from said virtualized translation table, and
generating said first physical memory address using said first memory bank and a second subset of said first virtualized memory address;
handling said first memory access request with a physical memory system using said first physical memory address, said handling comprising
destructively reading a first data word from said first physical memory address into a temporary register,
responding to said first memory access request with said first data word; and
storing said first data word back into said physical memory, said storing comprising
writing said first data word back into a second physical memory address, and
updating said virtualized translation table to associate said first virtualized memory address with said second physical memory address.
2. The method of handling memory access requests as set forth in claim 1 wherein said virtualized translation table has an equal number of rows as said set of N memory banks.
3. The method of handling memory access requests as set forth in claim 1 wherein entries in said virtualized translation table store a second subset of said first virtualized memory address.
4. The method of handling memory access requests as set forth in claim 1 wherein said first physical memory address space comprises N memory banks and said virtualized memory address space occupies a subset of said physical memory address space of a size of N-2 memory banks.
5. The method of handling memory access requests as set forth in claim 1 wherein said first memory access request comprises a read operation to a first bank in said physical memory, said method further comprising:
simultaneously receiving a second memory access request along with said first memory access request, said second memory access request comprising a write operation, said second memory access request identifying a second virtualized memory address in a virtualized memory address space;
writing to a new third physical memory address if a third physical address currently associated with said second virtualized memory address would cause a memory bank conflict with said first memory access request; and
updating said virtualized translation table to associate said first new physical memory address with said new third virtualized memory address.
6. A digital memory system for handing memory access requests, said digital memory system comprising:
a set of N independent physical memory banks; and
a memory system controller, said memory system controller comprising
a virtualized translation table,
a temporary register, and
control logic, said control logic translating virtualized memory addresses received in said memory access requests into physical memory addresses using said virtualized translation table, said control logic handling a first read request by translating a first virtualized address into a first physical memory address in said set of N independent physical memory banks, destructively reading a first data word from said first physical memory address into a temporary register, responding to said first read request with said first data word, and storing said first data word back into said set of N independent physical memory banks in a later memory cycle
wherein said control logic handles said first read request to said first virtualized address stored in a first memory bank while simultaneously handling a first write request to a second virtualized address stored in said first memory bank by writing data associated with said first write request to a second memory bank and updating said virtualized translation table to associate said second virtualized address with said second memory bank.
7. The digital memory system as set forth in claim 6 wherein said virtualized translation table is accessed using a first subset of said first virtualized address as an index and said virtualized translation table identifies a first memory bank from a set of N independent physical memory banks that currently represents said first virtualized memory address.
8. The digital memory system as set forth in claim 7 wherein said first subset of said first virtualized memory address and said first memory bank are used to construct said first physical address.
9. The digital memory system as set forth in claim 7 wherein said virtualized translation table has an equal number of rows as said set of N independent physical memory banks.
10. The digital memory system as set forth in claim 7 wherein entries in said virtualized translation table store a second subset of said first virtualized memory address.
11. The digital memory system as set forth in claim 7 , said digital memory system further comprising:
a temporary register row in said memory system controller, said temporary row register for storing a set of entries read from said a virtualized translation table upon receiving a memory read request to a first virtualized memory address,
wherein said control logic accesses said temporary register row if a memory write request to said first virtualized memory address is received a few clock cycles after said memory read request.
12. The digital memory system as set forth in claim 6 wherein said address space for said physical memory addresses comprises said N independent physical memory banks and said address space for said virtualized memory addresses occupies a subset of said physical memory address space of a size of N-2 memory banks.