Shielding 2-cycle half-page read and program schemes for advanced NAND flash design

1. A HiNAND memory sector circuit configured for a two-cycle half-page read scheme, the HiNAND memory sector circuit comprising:

M HiNAND blocks arranged in series in y-direction sharing a common P-well region and N global bit lines of BL[1] through BL[N] respectively for N strings in the y-direction, M being selected from 8, 16, 32, and more, N being an integer number of memory bit size, each HiNAND block comprising:

a plurality of memory cells built in the common P-well region and arranged as K pages in rows in x-direction plus one extra row of 2-poly NMOS select-gate flash cells and N strings in the columns in the y-direction, each page being associated with a word line, each string being associated with a local source line and a local bit line, each memory cell including one 2-poly NMOS floating gate transistor with its channel aligned in the y-direction, the x-direction being perpendicular to the y-direction, K being an integer selected from 32, 64, 128, and more;

a pair of global source lines CSL[o] and CSL[e] laid in the y-direction;

a first string decoder located at one end of the M HiNAND blocks, the first string decoder comprising a row of N 1-poly NMOS select-gate transistors having a first common gate input and respectively connecting corresponding drain nodes to the N global bit lines BL[1] through BL[N] and corresponding source nodes to the N local bit lines through all the M HiNAND blocks; and

a second string decoder located at another end of the M HiNAND blocks, the second string decoder comprising N/2 odd-column 1-poly NMOS select-gate transistors plus a first extra 1-poly NMOS select-gate transistor and N/2 even-column 1-poly NMOS select-gate transistors plus a second extra 1-poly NMOS select-gate transistor, the N/2 odd/even-column 1-poly NMOS select-gate transistors being respectively gated by a second/third common gate input for associating all N/2 odd/even-column strings with an odd/even group local source line LSL[o]/LSL[e] in the x-direction, the first/second extra 1-poly NMOS select-gate transistor being also gated by the second/third common gate input to control a coupling between the global source line CSL[o]/CSL[e] in the y-direction and the odd/even group local source line LSL[o]/LSL[e] in the x-direction;

wherein the first string decoder allows the N local bit lines of all odd-column and even-column strings of all the M HiNAND blocks being pre-charged to a bit line voltage Vbl in a pre-charge period of a half-page read operation and the second string decoder allows the odd-column strings in a selected page of the K pages of a selected block of the M HiNAND blocks being discharged in a data sensing period of the half-page read operation while the even-column strings in the selected page being retained at the pre-charged bit line voltage Vbl so as not be pulled down by the discharge of the odd-column strings to prevent the read of the odd-column strings from being affected by any coupling noise.

2. The HiNAND memory sector circuit of claim 1 further comprises an X-decoder circuit including at least a first control line, M groups of word lines, a second control line, and a third control line laid in the x-direction, the first/second/third control line connecting the first/second/third common gate input and each group of word lines including K word lines respectively connected to K pages of memory cells and a SG[0] line connected to the extra row of 2-poly NMOS select-gate flash cells for each block of the M HiNAND blocks.

3. The HiNAND memory sector circuit of claim 1 further comprises a low-voltage SA&PGM buffer circuit made from PMOS and NMOS devices with a power supply voltage Vdd, the low-voltage SA&PGM buffer circuit including least N+2 control lines in the y-direction respectively connected to the pair of global source lines CSL[o] and CSL[e] and all the N global bit lines BL[1] through BL[N] of the M HiNAND blocks.

4. The HiNAND memory sector circuit of claim 1 wherein the bit line voltage Vbl is a bias level smaller than a power supply voltage Vdd level minus a threshold voltage level of a corresponding memory cell.

5. The HiNAND memory sector circuit of claim 1 wherein each page of memory cells of a selected block of the M HiNAND blocks is read by performing a first cycle of odd/even-column half-page read operation and a second cycle of even/odd-column half-page read operation, each of the first cycle and the second cycle comprises a bias-condition setup period, a pre-charge period, and a data-sense period.

6. The HiNAND memory sector circuit of claim 5 wherein the bias-condition setup period for reading an odd-column half-page in the selected page of the selected block is associated with a first set of predetermined bias conditions including:

the Vdd level applied to the first common gate input;

a Vss=0V set for all K word lines including a corresponding SG[0] line in the selected block;

the Vss level set for all word lines including corresponding SG[0] lines of all M−1 unselected blocks;

the Vss level set for all the N global bit lines;

the Vss level set for the second common gate input;

the Vdd level applied to the third common gate input; and

the Vss level set for the pair of global source lines CSL[o] and CSL[e].

7. The HiNAND memory sector circuit of claim 6 wherein the pre-charge period for reading an odd-column half-page in the selected page in the selected block further is associated with a second set of predetermined bias conditions including:

the Vdd level applied to the first common gate input;

0 V applied to the selected word line associated with the selected page of the selected block;

the Vdd level applied to all K−1 non-selected word lines including the corresponding SG[0] line in the selected block;

the Vss level set for all word lines including the corresponding SG[0] lines in the M−1 unselected blocks;

the Vbl level applied to all the N global bit lines for charging both the local bit lines associated with N/2 odd-column strings and N/2 even-column strings, the Vbl level being smaller than the Vdd level;

the Vss level set for the second common gate input;

the Vdd level applied to the third common gate input;

the Vss level set for one of the pair of global source lines: CSL[o]; and

the Vdd level applied to another one of the pair of global source lines: CSL[e].

8. The HiNAND memory sector circuit of claim 7 wherein data-sensing period for reading an odd-column half-page in the selected page in the selected block further is associated with a third set of predetermined bias conditions including:

the Vdd level applied to the first common gate input;

a read voltage Vread level applied to the selected word line in the selected block;

a pass voltage Vpass level applied to all the K−1 non-selected word lines in the selected block, the Vpass level being set to 6.0V;

the Vdd level applied to the SG[0] line in the selected block;

the Vss level set for all word lines including the corresponding SG[0] lines in the M−1 unselected blocks;

the Vbl level kept at the N/2 global bit lines associated with the odd-column strings and further at corresponding N/2 local bit lines if a threshold voltage level of the selected cells is above the Vread level, or 0 V level discharged at the N/2 global bit lines associated with the odd-column strings and further at corresponding N/2 local bit lines if the threshold voltage level of the selected cells is below the Vread level;

the Vbl level kept at the N/2 global bit lines associated with even-column strings and further at the corresponding N/2 local bit lines;

the Vdd level applied to both the second common gate input and the third common gate input;

the Vss level set to the CSL[o]; and

the Vdd level applied to the CSL[e].

9. The HiNAND memory sector circuit of claim 5 wherein the bias-condition setup period of the second cycle of even/odd-column half-page read operation substantially follows the data sensing period of the first cycle of odd/even-column half-page read operation.

10. The HiNAND memory sector circuit of claim 8 wherein the read voltage Vread corresponds to one of four voltage levels: Vr0=0V, Vr1=1.5V, Vr2=2.5V, and Vr3=3.5V, applied to a selected multi-level memory cell having corresponding four threshold voltage levels of V t 0 of −2.0 V, V t 1 of ˜1V, V t 2 of ˜2V, and V t 3 of ˜3V.

11. The HiNAND memory sector circuit of claim 8 wherein the Vss level at the odd-column common source lines allows the odd group local source line at low for potentially discharging the local bit lines of the odd-column strings to 0V for reading stored data in the half-page memory cells associated with the selected word line and corresponding odd-column local bit lines, and the Vdd level at the even-column common source line is coupled to the even group local source line for retaining the local bit lines of the even-column strings at the Vbl level to induce a shielding effect for preventing a false-read of the odd-column strings.