IP Library Granted Patent US 9,014,508
Granted Patent B2
US 9,014,508 · App. 13/869,665 · Granted Apr 21, 2015

Multiplierless coprocessor for difference of Gaussian (DoG) calculation

Inventors: Mario Vigliar (Nocera Superiore, IT); Gian Domenico Licciardo (Montoro Inferiore, IT)
Assignee: STMicroelectronics S.r.l.
G06T5/50G06T5/003G06T1/20
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Quick Facts
Patent No.
US 9,014,508
App. No.
13/869,665
Granted
Apr 21, 2015
Kind
B2
Abstract

A hardware architecture is applied to the calculation of a Difference-of-Gaussian filter, which is typically employed in image processing algorithms. The architecture has a modular structure to easily allow the matching of the desired delay/area ratio as well as a high computational accuracy. A new solution is provided for the implementation of multiply-accumulators which allows a significant reduction of area with respect to the conventional architectures.

Claims (15)

1. A multiplier accumulator circuit comprising:

a first lookup table configured to provide Bachet terms in response to an input pixel value;

a plurality of second lookup tables configured to provide intermediate values in response to the Bachet terms; and

a set of full adders configured to sum the inte mediate values from the second lookup tables and to provide an output value representative of the input pixel value multiplied by a coefficient.

2. A multiplier accumulator circuit as defined in claim 1 , wherein the set of full adders is configured to add a further input value to the output value representative of the input pixel value multiplied by the coefficient.

3. A multiplier accumulator circuit as defined in claim 1 , configured for use in a Difference-of-Gaussian calculation, wherein the coefficient is a Gaussian coefficient.

4. A multiplier accumulator circuit as defined in claim 1 , wherein the input pixel value is an eight-bit data value.

5. A multiplier accumulator circuit as defined in claim 1 , wherein the plurality of second lookup tables includes six second lookup tables and wherein the set of full adders includes five full adders.

6. A multiplier accumulator circuit as defined in claim 2 , wherein the plurality of second lookup tables includes six second lookup tables and wherein the set of full adders includes six full adders.

7. A multiply accumulate method comprising:

providing Bachet terms from a first lookup table in response to an input pixel value;

providing intermediate values from a plurality of second lookup tables in response to the Bachet terms; and

summing the intermediate values with a set of full adders to provide an output value representative of the input pixel value multiplied by a coefficient.

8. A multiply accumulate method as defined in claim 7 , further comprising adding a further input value to the output value representative of the input pixel value multiplied by the coefficient.

9. A multiply accumulate method as defined in claim 7 , used in a Difference-of-Gaussian calculation, wherein the coefficient is a Gaussian coefficient.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2022
From: STMICROELECTRONICS S.R.L.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 060301/0355 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2013
From: VIGLIAR, MARIO; LICCIARDO, GIAN DOMENICO
To: STMICROELECTRONICS S.R.L.
Reel/Frame 030852/0234 →
Continuity (2)
Provisional Application 61637504 · Apr 24, 2012
Related Publication 20130301950A1 · Nov 14, 2013