Interruptible write block
A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.
1. A memory device having an interruptible write block comprising:
a primary register having an input coupled to an input of said interruptible write block and an output coupled to a first output of said interruptible write block;
a secondary register having an input coupled to an output of an interrupt circuit;
said interrupt circuit being configured to interrupt flow of new data from said output of said primary register to said input of said secondary register during an interrupt of a write operation, such that upon resumption of said write operation said secondary register contains valid data for a second output of said interruptible write block.
2. The memory device of claim 1 , wherein said output of said interrupt circuit is selectably coupled to said output of said primary register.
3. The memory device of claim 1 , wherein said output of said interrupt circuit is selectably coupled to an output of said secondary register.
4. The memory device of claim 1 , wherein said interrupt circuit comprises an interrupt multiplexer.
5. The memory device of claim 4 , wherein a select line of said interrupt multiplexer is utilized to interrupt said flow of said new data from output of said primary register to said input of said secondary register during said interrupt of said write operation.
6. The memory device of claim 1 , wherein said interruptible write block is utilized to reduce the number of inputs to a memory array in said memory device.
7. The memory device of claim 1 , wherein said memory device comprises a CAM (content addressable memory).
8. The memory device of claim 1 , wherein said memory device comprises a RAM (random access memory).
9. The memory device of claim 1 , wherein said memory device comprises a scannable output reduction block.
10. A method of utilizing an interruptible write block in a memory device, said method comprising:
loading data received at an input of said interruptible write block into a primary register;
providing said data from an output of said primary register to a first output of said interruptible write block during a write operation;
loading said data into an input of a secondary register from said output of said primary register;
interrupting flow of new data from said output of said primary register to said input of said secondary register during an interrupt of said write operation to perform a desired operation in said memory device;
resuming said write operation using said data from said secondary register at a second output of said interruptible write block.
11. The method of claim 10 further comprising loading additional data into said primary register prior to resuming said write operation.
12. The method of claim 10 , comprising utilizing said interruptible write block to reduce the number of inputs to a memory array in said memory device.
13. The method of claim 10 , wherein said memory device comprises a CAM (content addressable memory).
14. The method of claim 10 , wherein said memory device comprises a RAM (random access memory).
15. The method of claim 10 , wherein said memory device comprises a scannable output reduction block.
16. The method of claim 11 , wherein said interrupt of said write operation is implemented using an interrupt multiplexer.
17. The method of claim 10 , wherein a select line of an interrupt multiplexer is utilized to cause said interrupting said flow of said new data from said output of said primacy register to said input of said secondary register during said interrupt of said write operation.