Co-packaging photonic integrated circuits and application specific integrated circuits
View Patent ↗Disclosed herein are designs, structures and techniques for advanced packaging of multi-function photonic integrated circuits that allow such high-performance multi-function photonic integrated circuits to be co-packaged with a high-performance multi-function ASIC thereby significantly reducing strenuous interconnect challenges and lowering costs, power and size of the overall devices.
1. A co-packaging arrangement comprising:
a photonic integrated circuit (PIC) and an application specific integrated circuit (ASIC) positioned beside the PIC, wherein the PIC and the ASIC are disposed on a substrate within a housing;
wherein the PIC is edge-coupled to an optical fiber, and wherein the PIC comprises one or more optical modulators and one or more optical detectors;
wherein the substrate comprises electrical interconnects configured to electrically connect the PIC to the ASIC; and
wherein the one or more optical modulators are driven directly from a digital-to-analog converter (DAC) that is located on the ASIC.
2. The co-packaging arrangement according to claim 1 , wherein a transimpedance amplifier (TIA), electrically coupled to the one or more optical detectors, is located on the ASIC with no active electrical elements in-between the one or more optical detectors and the TIA.
3. The co-packaging arrangement according to claim 1 , wherein the ASIC comprises a driver amplifier electrically coupled to the one or more optical modulators such that there is no active electrical element between the one or more optical modulators and the driver amplifier.
4. A co-packaging arrangement comprising:
a photonic integrated circuit (PIC) and an application specific integrated circuit (ASIC) positioned beside the PIC, wherein the PIC and the ASIC are disposed on a substrate within a housing;
wherein the PIC comprises a coherent transceiver having one or more optical modulators driven directly from a digital-to-analog converter (DAC) that is located on the ASIC; and
a tunable laser disposed outside of the housing, such that there are no cooling devices within the housing.
5. The co-packaging arrangement of claim 1 , wherein the PIC comprises a number of high-speed Input/Output connectors positioned along one single edge of the PIC.
6. The co-packaging arrangement of claim 1 , further comprising a thermal conductor placed in contact with the ASIC.
7. The co-packaging arrangement of claim 1 , wherein the housing comprises a heat sink overlying a top surface of the housing, wherein the housing has an opening through which the optical fiber passes.
8. The co-packaging arrangement of claim 1 , wherein the PIC is coupled to the substrate through die bonds, and wherein the die bonds are connected to through silicon vias (TSVs) disposed within the PIC.
9. The co-packaging arrangement of claim 1 , wherein the ASIC is flip-chip mounted and die bonded to the substrate.
10. The co-packaging arrangement of claim 1 , further comprising a v-groove assembly, wherein the optical fiber is disposed, at least in part, on a v-groove of the v-groove assembly.
11. The co-packaging arrangement of claim 1 , wherein the PIC includes a horizontal mode-converter and a horizontal optical waveguide, the horizontal mode converter being disposed between the optical fiber and the horizontal optical waveguide.
12. The co-packaging arrangement of claim 4 , wherein the PIC is coupled to an optical fiber, and wherein the co-packaging arrangement further comprises a v-groove assembly, wherein the optical fiber is disposed, at least in part, on a v-groove of the v-groove assembly.
13. The co-packaging arrangement of claim 4 , wherein the ASIC comprises a driver amplifier electrically coupled to the one or more optical modulators such that there is no active electrical element between the one or more optical modulators and the driver amplifier.
14. The co-packaging arrangement of claim 4 , wherein the PIC comprises a number of high-speed Input/Output connectors positioned along one single edge of the PIC.
15. The co-packaging arrangement of claim 4 , wherein the housing comprises a heat sink overlying a top surface of the housing, wherein the housing has an opening through which an optical fiber passes.
16. The co-packaging arrangement of claim 4 , wherein the PIC is coupled to the substrate through die bonds, and wherein the die bonds are connected to through silicon vias (TSVs) disposed within the PIC.