Semiconductor device having high-frequency interconnect
View Patent ↗Provided is a semiconductor device including high-frequency interconnect and dummy conductor patterns (second dummy conductor patterns). The dummy conductor patterns are disposed in a interconnect layer different from a interconnect layer in which the high-frequency interconnect is disposed. The dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in plan view. The semiconductor device further includes dummy conductor patterns (first dummy conductor patterns) in the interconnect layer in which the high-frequency interconnect is disposed.
1. A semiconductor device comprising:
a high-frequency interconnect disposed in a first layer in an interconnect layer;
a plurality of first dummy conductor patterns disposed in the interconnect layer; and
a plurality of second dummy conductor patterns disposed in a second layer which is different from the first layer in the interconnect layer,
wherein the second dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in a plan view,
wherein the high-frequency interconnect includes an inductor having a coil shape,
wherein the first dummy conductor patterns and the second dummy conductor patterns are formed on an inner side of a region surrounded by the high-frequency interconnect in a plan view such that the first dummy conductor patterns and the second dummy conductor patterns are overlapped, at least a part thereof, with each other, and
wherein the first dummy conductor patterns and the second dummy conductor patterns form an open circuit.
2. The semiconductor device according to claim 1 , wherein the high-frequency interconnect is configured to permit flow of an electric current with a frequency of at least 5 GHz.
3. The semiconductor device according to claim 1 , wherein the high-frequency interconnect comprises the inductor and an extraction interconnect that is electrically connected to the inductor.
4. The semiconductor device according to claim 1 , wherein the second dummy conductor patterns are formed on both of the inner side and an outer side of the region surrounded by the high-frequency interconnect in the plan view.
5. The semiconductor device according to claim 1 ,
wherein the second dummy conductor patterns are formed on both sides of the high-frequency interconnect in the plan view.
6. The semiconductor device according to claim 1 , wherein
the second layer abuts the first layer.
7. The semiconductor device according to claim 1 , wherein the second layer is formed below the first layer, and
wherein a minimum value of a distance between each of the first dummy conductor patterns and the high-frequency interconnect is larger than a distance between a plain surface, which contains a top surface of each of the second dummy conductor patterns, and the high-frequency interconnect.
8. The semiconductor device according to claim 1 , wherein:
the second layer is formed above the first layer; and
a minimum value of a distance between each of the first dummy conductor patterns and the high-frequency interconnect is larger than a distance between a plain surface, which contains a bottom surface of each of the second dummy conductor patterns, and the high-frequency interconnect.
9. The semiconductor device according to claim 1 ,
wherein a minimum value of a distance between each of the first dummy conductor patterns and the high-frequency interconnect is larger than a minimum value of a distance between each of the second dummy conductor patterns and the high-frequency interconnect.
10. The semiconductor device according to claim 1 , further comprising:
a substrate; and
a transistor formed on the substrate,
wherein the interconnect layer is formed over the transistor.
11. The semiconductor device according to claim 1 , wherein
the second dummy conductor patterns form an open circuit.
12. The semiconductor device according to claim 1 ,
wherein the second dummy conductor patterns are arranged in a form of dot pattern.
13. The semiconductor device according to claim 1 , wherein
the second layer is formed below the first layer, and
a minimum value of a distance between each of the first dummy conductor patterns and the high-frequency interconnect is larger than a distance between a plain surface, which contains a top surface of each of the second dummy conductor patterns, and the high-frequency interconnect,
whereby eddy currents generated in the conductor patterns are suppressed.
14. The semiconductor device according to claim 13 , wherein
the distance between the plain surface, which contains a top surface of each of the second dummy conductor patterns, and the high-frequency interconnect, is equal to a distance between a plain surface containing bottom surfaces of the dummy conductor patterns and the high frequency interconnect.
15. A semiconductor device comprising:
a high-frequency interconnect disposed in a first layer in an interconnect layer, the high-frequency interconnect being configured to conduct an electric current with a frequency of at least 5 GHz;
a plurality of first dummy conductor patterns disposed in the interconnect layer; and
a plurality of second dummy conductor patterns disposed in a second layer which is different from the first layer in the interconnect layer,
wherein the second dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in a plan view,
the high-frequency interconnect includes an inductor having a coil shape, the inductor being configured to generate a magnetic field,
the first dummy conductor patterns and the second dummy conductor patterns are formed on an inner side of a region surrounded by the high-frequency interconnect in a plan view such that the first dummy conductor patterns and the second dummy conductor patterns are overlapped, at least a part thereof, with each other,
the first dummy conductor patterns and the second dummy conductor patterns form an open circuit,
the second layer is formed below the first layer, and
a minimum value of a distance between each of the first dummy conductor patterns and the high-frequency interconnect is larger than a distance between a plain surface, which contains a top surface of each of the second dummy conductor patterns, and the high-frequency interconnect,
whereby eddy currents generated in the conductor patterns are suppressed.
16. The semiconductor device according to claim 15 , wherein the high-frequency interconnect comprises the inductor and an extraction interconnect that is electrically connected to the inductor.
17. The semiconductor device according to claim 15 , wherein the second dummy conductor patterns are formed on both of the inner side and an outer side of the region surrounded by the high-frequency interconnect in the plan view.
18. The semiconductor device according to claim 15 ,
wherein the second dummy conductor patterns are formed on both sides of the high-frequency interconnect in the plan view.
19. The semiconductor device according to claim 1 , wherein
the second layer abuts the first layer.
20. A semiconductor device comprising:
a high-frequency interconnect disposed in a first layer in an interconnect layer, the high-frequency interconnect being configured to conduct an electric current with a frequency of at least 5 GHz;
a plurality of first dummy conductor patterns disposed in the interconnect layer; and
a plurality of second dummy conductor patterns disposed in a second layer which is different from the first layer in the interconnect layer, the first and second dummy conductor patterns being formed of a same damascened material as the high-frequency interconnect,
wherein the second dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in a plan view,
the high-frequency interconnect includes an inductor having a coil shape, the inductor being configured to generate a magnetic field,
the first dummy conductor patterns and the second dummy conductor patterns are formed on an inner side of a region surrounded by the high-frequency interconnect in a plan view such that the first dummy conductor patterns and the second dummy conductor patterns are overlapped, at least a part thereof, with each other,
the first dummy conductor patterns and the second dummy conductor patterns form an open circuit,
the second layer is formed below the first layer, and
a minimum value of a distance between each of the first dummy conductor patterns and the high-frequency interconnect is larger than a distance between a plain surface, which contains a top surface of each of the second dummy conductor patterns, and the high-frequency interconnect,
whereby eddy currents generated in the conductor patterns are suppressed.