Semiconductor device with electrical overstress (EOS) protection
View Patent ↗A semiconductor device with electrical overstress (EOS) protection is disclosed. The semiconductor device includes a semi-insulating layer, a first contact disposed onto the semi-insulating layer, and a second contact disposed onto the semi-insulating layer. A passivation layer is disposed onto the semi-insulating layer. The passivation layer has a dielectric strength that is greater than that of the semi-insulating layer to ensure that a voltage breakdown occurs within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer.
1. A semiconductor device with electrical overstress (EOS) protection comprising:
a semiconductor element having a gate, an input terminal, and an output terminal; and
an EOS protection device comprising;
a semi-insulating layer;
a first contact embedded in the semi-insulating layer and coupled to the input terminal;
a second contact embedded in the semi-insulating layer and coupled to the output terminal; and
a passivation layer disposed directly onto the semi-insulating layer such that opposing vertical sides of the first contact and the second contact directly abut both the passivation layer and the semi-insulating layer while leaving the first contact and the second contact uncovered with a gap between the first contact and the second contact set to provide a predetermined avalanche breakdown voltage level and wherein a dielectric strength of the passivation layer is greater than that of the semi-insulating layer to ensure that an avalanche voltage breakdown occurs at the predetermined avalanche breakdown voltage level within the semi-insulating layer within a semi-insulating region between the first contact and the second contact before a voltage breakdown can occur in the passivation layer, wherein the semi-insulating region is laterally spaced from the gate such that the gate does not overlap the semi-insulating region.
2. The semiconductor device of claim 1 wherein a predetermined resistivity of the semi-insulating region prevents leakage current from rising to a level greater than an intrinsic drain-to-source leakage of the semiconductor device being protected.
3. The semiconductor device of claim 1 further including an epitaxial layer disposed onto the semi-insulating layer.
4. The semiconductor device of claim 3 wherein the epitaxial layer extends between the first contact and the second contact.
5. The semiconductor device of claim 3 wherein the epitaxial layer is made of gallium nitride (GaN) and the semi-insulating layer is a substrate made of the same material as the semi-insulating region.
6. The semiconductor device of claim 1 further including a transformed region within the semi-insulating region.
7. The semiconductor device of claim 6 wherein the transformed region comprises implanted ions.
8. The semiconductor device of claim 7 wherein the implanted ions are selected from a group consisting of aluminum, argon, boron, silicon, phosphorus, arsenic, gallium, and nitrogen.
9. The semiconductor device of claim 6 wherein either the first contact or the second contact at least partially overlaps the transformed region.
10. The semiconductor device of claim 6 wherein both the first contact and the second contact at least partially overlap the transformed region.
11. The semiconductor device of claim 6 wherein neither of the first contact and the second contact overlaps the transformed region.
12. The semiconductor device of claim 1 further including at least one field plate coupled to at least the first contact or the second contact.
13. The semiconductor device of claim 1 wherein the first contact, the second contact, and the semi-insulating region comprise an EOS protection device in which at least one of the first contact and the second contact are co-located with the drain and source, respectively.
14. The semiconductor device of claim 1 wherein the first contact, the second contact, and the semi-insulating layer comprise an EOS protection device in which the first contact and the second contact are coupled to the drain and source, respectively, without sharing a common substrate.
15. The semiconductor device of claim 1 wherein the first contact, the second contact, and the semi-insulating layer comprise an EOS protection device that is located on a wafer backside that includes vias for coupling the first contact and the second contact to the drain and source, respectively.
16. The semiconductor device of claim 1 wherein the drain includes a plurality of drain fingers, the gate includes a plurality of gate fingers, and the source includes a plurality of source fingers.
17. The semiconductor device of claim 16 wherein a plurality of EOS protection devices each made of a first contact, a second contact, and a semi-insulating layer coupled between each of the drain fingers and source fingers, respectively.
18. The semiconductor device of claim 1 wherein the semiconductor device is a high voltage diode.
19. The semiconductor device of claim 1 wherein the first contact and the second contact are recessed within a substrate making up the semi-insulating layer.
20. The semiconductor device of claim 1 wherein the first contact and the second contact are in contact with and on opposing vertical sides of a substrate making up the semi-insulating layer.
21. The semiconductor device of claim 1 wherein the first contact and the second contact are in contact with opposing vertical sides of an epitaxial layer making up the semi-insulating layer.