Leakage compensation for switched capacitor integrators
View Patent ↗Methods and systems for a differential correlated double sampling (CDS) switched capacitor integrator circuit. The circuit includes a differential amplifier that has a differential input and a differential output. There is a first feedback path between the negative output node and the positive input node, and a second feedback path between the positive output node and the negative input node. Each feedback path includes an integration capacitor and at least one switch that has a parasitic capacitance. A first capacitive element is coupled between the negative input node and the negative output node, and a second capacitive element is coupled between the positive input node and the positive output node. Each capacitive element is configured to cancel the parasitic capacitance of its corresponding feedback path.
1. A differential correlated double sampling (CDS) switched capacitor integrator circuit, comprising:
a differential amplifier, comprising:
a differential input having a negative and a positive input node;
a differential output having a negative and a positive output node;
a first feedback path between the positive output node and the negative input node, comprising:
an integration capacitor; and
at least one switch having a parasitic capacitance;
a second feedback path between the negative output node and the positive input node, comprising:
an integration capacitor; and
at least one switch having a parasitic capacitance;
a first capacitive element coupled between the negative input node and the negative output node and configured to cancel the parasitic capacitance of the at least one switch of the first feedback path; and
a second capacitive element coupled between the positive input node and the positive output node and configured to cancel the parasitic capacitance of the at least one switch of the second feedback path.
2. The circuit of claim 1 , wherein:
the first capacitive element is a dummy switch that has a total capacitance of the at least one switch in the first feedback path; and
the second capacitive element is a dummy switch that has a total capacitance of the at least one switch in the second feedback path.
3. The circuit of claim 2 , wherein each switch and dummy switch is a metal oxide semiconductor field effect transistor (MOSFET).
4. The circuit of claim 3 , wherein a drain to source capacitance of each dummy MOSFET switch has the total capacitance of the at least one switch in the first feedback path.
5. The circuit of claim 1 , wherein:
the first and second capacitive elements are configured to track the parasitic capacitance of the at least one switch in the first and second feedback paths, respectively, over at least one of:
(i) a process change;
(ii) a temperature change; and
(iii) an aging of the circuit.
6. The circuit of claim 1 , wherein:
a charge stored in the first capacitive element is equal in magnitude but opposite in polarity to a charge lost due to charge sharing between the integration capacitor and the at least one switch in the first feedback path; and
a charge stored in the second capacitive element is equal in magnitude but opposite in polarity to a charge lost due to charge sharing between the integration capacitor and the at least one switch in the second feedback path.
7. The circuit of claim 1 , wherein:
the at least one switch in the first feedback path comprises:
a first switch coupled between the positive output node and the negative input node; and
a second switch coupled in series between the first input node and the integration capacitor; and
the at least one switch in the second feedback path comprises:
a first switch coupled between the negative output node and the positive input node; and
a second switch coupled in series between the second input node and the integration capacitor.
8. The circuit of claim 7 , wherein in both the first and the second feedback paths, the first and second switches are of equal size and have the same parasitic capacitance.
9. The circuit of claim 8 , wherein:
the first capacitive element has a capacitance equal to twice the parasitic capacitance of the first switch of the first feedback path; and
the second capacitive element has a capacitance equal to twice the parasitic capacitance of the first switch of the second feedback path.
10. The circuit of claim 8 , wherein a capacitance of the first and second capacitive elements are equal.
11. The circuit of claim 3 , wherein a channel width of the first and second dummy MOSFET switches is each twice a channel width of the at least one switch of the first and second feedback path, respectively.
12. The circuit of claim 3 , wherein the first and second dummy MOSFET switches each comprise a pair of MOSFETs having a same size as the at least one switch in the first feedback path.
13. A method of canceling the parasitic capacitance of at least one switch in a first and second feedback paths in a differential correlated double sampling (CDS) switched capacitor integrator circuit that includes a differential amplifier comprising the first feedback path between a positive output node and a negative input node, comprising an integration capacitor and at least one switch having a parasitic capacitance; and the second feedback path between the negative output node and the positive input node, comprising an integration capacitor and at least one switch having a parasitic capacitance, the method comprising:
compensating a charge lost due to a charge sharing between the integration capacitor and the at least one switch in the first feedback path and the second feedback path, respectively;
adding a first charge that is equal in magnitude but opposite in polarity to the charge lost in the first feedback path; and
adding a second charge that is equal in magnitude but opposite in polarity to the charge lost in the second feedback path.