Method and system for selective power control for a multi-media processor
View Patent ↗A method and system for controlling power is provided. The system is configured to selectively control a plurality of power control domains. The system may be configured to process audio data in at least one of the domains. The system may be configured to output audio data, while one or more of the power control domains is suspended.
1. A method for controlling power, the method comprising:
in an integrated circuit comprising a multimedia processor, said multimedia processor comprising an audio interface and a processing unit:
decoding coded audio data with the processing unit to generate decoded audio data;
storing the decoded audio in memory;
powering down the processing unit; and
providing, with the audio interface, the decoded audio data from the memory to an output, while the processing unit is powered down
powering up the processing unit in response to an amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.
2. The method according to claim 1 , further comprising storing processor states for the processing unit in memory, before powering down the processing unit.
3. The method according to claim 1 , wherein the processing unit is powered down in response to a first amount of audio data being decoded.
4. The method according to claim 1 , further comprising retrieving stored processor states from the memory in response to the amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.
5. The method according to claim 1 , wherein the processing unit is a video processing core and power is removed from the entire video processing core during power down.
6. The method according to claim 4 , further comprising decoding a burst of coded audio data in response to the amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.
7. The method according to claim 4 , further comprising storing processor states for the processing unit in memory, before powering down the processing unit.
8. A method for controlling power, the method comprising:
in an integrated circuit comprising a multimedia processor, said multimedia processor comprising an audio interface and a processing unit, wherein the processing unit includes a vector processing unit, a graphics processing unit, and a video coder:
decoding coded audio data with the processing unit to generate decoded audio data;
storing the decoded audio in memory;
powering down the processing unit; and
providing, with the audio interface, the decoded audio data from the memory to an output, while the processing unit is powered down wherein the processing unit includes a vector processing unit, a graphics processing unit, and a video coder.
9. A method for controlling power, the method comprising:
in an integrated circuit comprising a multimedia processor, said multimedia processor comprising an audio interface and a processing unit, wherein the processing unit is a video processing core and power is removed from the entire video processing core during power down:
decoding coded audio data with the processing unit to generate decoded audio data;
storing the decoded audio in memory;
powering down the processing unit; and
providing, with the audio interface, the decoded audio data from the memory to an output, while the processing unit is powered down wherein the processing unit includes a vector processing unit, a graphics processing unit, and a video coder.
10. A system for controlling power, the system comprising:
an integrated circuit including a multimedia processor having a plurality of power control domains, each power control domain being configured for independent power control from each other power control domain of the plurality of power domains, the plurality of power control domains comprising an interface domain configured to process audio output while each other power control domain is suspended, wherein the plurality of power control domains includes an image domain and the interface domain is configured to process the audio output while the image domain is suspended.
11. The system according to claim 10 , wherein the plurality of power control domains includes a graphics domain and the interface domain is configured to process the audio output while the graphics domain is suspended.
12. A system for controlling power, the system comprising:
an integrated circuit including a multimedia processor having a plurality of power control domains, each power control domain being configured for independent power control from each other power control domain of the plurality of power domains, the plurality of power control domains comprising an interface domain configured to process audio output while each other power control domain is suspended, wherein the plurality of power control domains includes a graphics domain and the interface domain is configured to process the audio output while the graphics domain is suspended.
13. A system for controlling power, the system comprising:
an integrated circuit including a multimedia processor having a plurality of power control domains, each power control domain being configured for independent power control from each other power control domain of the plurality of power domains, the plurality of power control domains comprising an interface domain configured to process audio output while each other power control domain is suspended, wherein the plurality of power control domains includes an audio domain and the interface domain is configured to process the audio output while the audio domain is suspended.
14. The system according to claim 13 , wherein power is removed from the audio domain while the audio domain is suspended.
15. The system according to claim 14 , wherein audio domain comprises a vector processing unit, a direct memory access controller, and a display driver.
16. The system according to claim 13 , wherein the audio domain includes a processing unit for decoding audio data.
17. The system according to claim 16 , wherein the processing unit is configured to store processor states in memory, before suspension of the audio domain.
18. The system according to claim 17 , wherein the audio domain is suspended in response to a first amount of audio data being decoded.
19. The system according to claim 18 , wherein the audio domain configured to wake-up in response to an amount of decoded audio data to be transferred falling below a threshold amount of decoded audio data.
20. The system according to claim 19 , wherein the processing unit is configured to retrieve processor states in response to audio domain waking-up.