IP Library Granted Patent US 8,861,906
Granted Patent B2
US 8,861,906 · App. 13/873,771 · Granted Oct 14, 2014

Method and system for coupling optical signals into silicon optoelectronic chips

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Quick Facts
Patent No.
US 8,861,906
App. No.
13/873,771
Granted
Oct 14, 2014
Kind
B2
Abstract

A method and system for coupling optical signals into silicon optoelectronic chips are disclosed and may include coupling one or more optical signals into a back surface of a CMOS photonic chip in a photonic transceiver, wherein photonic, electronic, or optoelectronic devices may be integrated in a front surface of the CMOS photonic chip. Optical couplers, such as grating couplers, may receive the optical signals in the front surface of the chip. The optical signals may be coupled into the back surface of the chips via optical fibers and/or optical source assemblies. The optical signals may be coupled to the optical couplers via a light path etched in the chips, which may be refilled with silicon dioxide. The chips may be flip-chip bonded to a packaging substrate. Optical signals may be reflected back to the optical couplers via metal reflectors, which may be integrated in dielectric layers on the chips.

Claims (23)

1. A method for processing signals, the method comprising:

in a photonic transceiver comprising a CMOS photonic chip, coupling one or more optical signals into a back surface of said CMOS photonic chip, wherein photonic, electronic, or optoelectronic devices are integrated in a front surface of said CMOS photonic chip and one or more optical couplers receive said one or more optical signals in said front surface of said CMOS photonic chip.

2. The method according to claim 1 , comprising coupling said one or more optical signals into said back surface of said CMOS photonic chip via one or more optical fibers.

3. The method according to claim 1 , wherein said optical couplers comprise grating couplers.

4. The method according to claim 1 , comprising coupling said one or more optical signals into said back surface of said CMOS photonic chip via one or more optical source assemblies.

5. The method according to claim 1 , comprising coupling said one or more optical signals to said one or more grating couplers via a light path etched in said CMOS photonic chip.

6. The method according to claim 5 , wherein said etched light path is refilled with silicon dioxide.

7. The method according to claim 1 , wherein said CMOS photonic chip is flip-chip bonded to a packaging substrate.

8. The method according to claim 1 , comprising reflecting optical signals that pass through said one or more optical couplers back to said one or more optical couplers via one or more metal reflectors.

9. The method according to claim 8 , wherein said one or more metal reflectors are integrated in dielectric layers on said CMOS photonic chip.

10. A system for processing signals, the system comprising:

a photonic transceiver comprising a CMOS photonic chip with photonic, electronic, or optoelectronic devices integrated in a front surface of said CMOS photonic chip, wherein one or more optical signals are coupled into a back surface of said CMOS photonic chip, and one or more optical couplers receive said one or more optical signals in said front surface of said CMOS photonic chip.

11. The system according to claim 10 , wherein said one or more optical signals are coupled into said back surface of said CMOS photonic chip via one or more optical fibers.

12. The system according to claim 11 , wherein said one or more optical fibers is affixed to said CMOS photonic chip using epoxy.

13. The system according to claim 10 , wherein said optical couplers comprise grating couplers.

14. The system according to claim 10 , wherein said photonic, electronic, or optoelectronic devices are operable to couple said one or more optical signals into said back surface of said CMOS photonic chip via one or more optical source assemblies.

15. The system according to claim 10 , wherein said photonic, electronic, or optoelectronic devices are operable to couple said one or more optical signals to said one or more optical couplers via a light path etched in said CMOS photonic chip.

16. The system according to claim 15 , wherein said etched light path is refilled with silicon dioxide.

17. The system according to claim 10 , wherein said CMOS photonic chip is flip-chip bonded to a packaging substrate.

18. The system according to claim 10 , wherein said photonic, electronic, or optoelectronic devices are operable to reflect optical signals that pass through said one or more grating couplers back to said one or more grating couplers via one or more metal reflectors.

19. The system according to claim 18 , wherein said one or more metal reflectors are integrated in dielectric layers on said CMOS photonic chip.

20. A system for processing signals, the system comprising:

a photonic transceiver comprising a CMOS photonic chip with photonic, electronic, or optoelectronic devices integrated beneath a stack of dielectric layers in a front surface of said CMOS photonic chip, wherein said front surface of said CMOS photonic chip is flip-chip bonded to a packaging substrate; and wherein one or more optical couplers integrated beneath a metal reflector embedded in said dielectric layers receive one or more optical signals coupled into a back surface of said CMOS photonic chip.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
RELEASE OF SECURITY INTEREST Recorded Dec 24, 2020
From: SILICON VALLEY BANK
To: LUXTERA, LLC
Reel/Frame 054855/0838 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →
SECURITY INTEREST Recorded Mar 29, 2017
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 042109/0140 →
SECURITY INTEREST Recorded Mar 20, 2015
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 035219/0546 →