Variable resistance non-volatile memory device and manufacturing method thereof

1. A method of manufacturing a variable resistance non-volatile memory device including non-volatile memory element layers stacked together by repeating a step of forming a non-volatile memory element layer plural times,

the step of forming the non-volatile memory element layer including steps of:

forming a lower electrode layer;

forming a variable resistance layer on and above the lower electrode layer; and

forming an upper electrode layer on and above the variable resistance layer; and

the step of forming the variable resistance layer including steps of:

forming a first metal oxide layer comprising a first metal oxide; and

forming a second metal oxide layer comprising a second metal oxide having a higher oxygen content atomic percentage than the first metal oxide, wherein:

when a thickness of the second metal oxide layer included in each of the non-volatile memory element layers just after the step of forming a corresponding non-volatile memory element layer is completed is a thickness in formation, and

when an area of a portion of the second metal oxide layer included in each of the non-volatile memory element layers and a portion of the first metal oxide layer included in a corresponding non-volatile memory element layer, which portions are in contact with each other, just after the step of forming the corresponding non-volatile memory element layer is completed is an area in formation,

at least one of the thickness in formation and the area in formation is made different among the steps of forming the non-volatile memory element layers, to cause all of the non-volatile memory element layers in a state in which formation of an uppermost non-volatile memory element layer is completed, to have an equal initial resistance.

2. The method of manufacturing the variable resistance non-volatile memory device according to claim 1 ,

wherein by diffusion of oxygen including diffusion of oxygen from the second metal oxide layer to the first metal oxide layer, in the steps of forming all of the non-volatile memory element layers, at least one of the thickness in formation and the area in formation is made different, among the steps of forming the non-volatile memory element layers, to cause all of the non-volatile memory element layers, in a state in which formation of the uppermost non-volatile memory element layer is completed, to have an equal initial resistance.

3. The method of manufacturing the variable resistance non-volatile memory device according to claim 1 ,

wherein the thickness in formation is greater in the step corresponding to a lower non-volatile memory element layer, among the steps of forming the non-volatile memory element layers.

4. The method of manufacturing the variable resistance non-volatile memory device according to claim 3 ,

wherein when the thickness in formation in the step of forming a lower non-volatile memory element layer is D1 and the thickness in formation in the step of forming an upper non-volatile memory element layer is D2, regarding a combination of two steps of forming the non-volatile memory element layers, which occur successively, among the steps of forming the non-volatile memory element layers,

D2<D1<(1.1×D2) is satisfied.

5. The method of manufacturing the variable resistance non-volatile memory device according to claim 1 ,

wherein the step of forming the non-volatile memory element layer includes the step of forming a third metal oxide layer comprising a third metal oxide having a higher oxygen content atomic percentage than the first metal oxide, on an outer peripheral portion of the first metal oxide layer such that the second metal oxide layer is interposed between the first metal oxide layer and the third metal oxide layer, and the electrode.

6. The method of manufacturing the variable resistance non-volatile memory device according to claim 5 ,

wherein in the step corresponding to a lower non-volatile memory element layer, among the steps of forming the non-volatile memory element layers, an area of a portion of the third metal oxide layer and a portion of the second metal oxide layer, which portions are in contact with each other, just after the step of forming the corresponding non-volatile memory element layer is completed, is smaller.

7. The method of manufacturing the variable resistance non-volatile memory device according to claim 5 ,

wherein in the step corresponding to a lower non-volatile memory element layer, among the steps of forming the non-volatile memory element layers, an area of the upper electrode layer, just after the step of forming the corresponding non-volatile memory element layer is completed, is greater.

8. The method of manufacturing the variable resistance non-volatile memory device according to claim 1 ,

wherein the step of forming the non-volatile memory element layer includes the step of forming an oxygen barrier layer on a side wall of the variable resistance layer.

9. The method of manufacturing the variable resistance non-volatile memory device according to claim 1 ,

wherein in the step corresponding to a lower non-volatile memory element layer, among the steps of forming the non-volatile memory element layers, the area in formation is greater.

10. The method of manufacturing the variable resistance non-volatile memory device according to claim 1 ,

wherein a step accompanied by heating, other than a deposition step and an etching step, is performed after the step of forming the uppermost non-volatile memory element layer is completed.

11. A variable resistance non-volatile memory device comprising non-volatile memory element layers stacked together,

each of the non-volatile memory element layers including a lower electrode layer, a variable resistance layer formed on and above the lower electrode layer, and an upper electrode layer formed on and above the variable resistance layer,

the variable resistance layer including a first metal oxide layer comprising a first metal oxide, and a second metal oxide layer comprising a second metal oxide having a higher oxygen content atomic percentage than the first metal oxide, wherein:

when a thickness of the second metal oxide layer included in each of the non-volatile memory element layers just after formation of the corresponding non-volatile memory element layer is completed is a thickness in formation, and

when an area of a portion of the second metal oxide layer included in each of the non-volatile memory element layers and a portion of the first metal oxide layer included in the corresponding non-volatile memory element layer, which portions are in contact with each other, just after formation of the corresponding non-volatile memory element layer is completed is an area in formation,

at least one of the thickness in formation and the area in formation is made different among the non-volatile memory element layers, to cause all of the non-volatile memory element layers to have an equal initial resistance.

12. The variable resistance non-volatile memory device according to claim 11 ,

wherein all of the non-volatile memory element layers are caused to have an equal initial resistance, by diffusion of oxygen including diffusion of oxygen from the second metal oxide layer to the first metal oxide layer, in the steps of forming all of the non-volatile memory element layers.

13. The variable resistance non-volatile memory device according to claim 11 ,

wherein the thickness in formation is greater in a lower non-volatile memory element layer.

14. The variable resistance non-volatile memory device according to claim 13 ,

wherein when the thickness in formation in a lower non-volatile memory element layer is D1 and the thickness in formation in an upper non-volatile memory element layer is D2, regarding a combination of two non-volatile memory element layers which are adjacent to each other,

D2<D1<(1.1×D2) is satisfied.

15. The variable resistance non-volatile memory device according to claim 11 ,

wherein the variable resistance layer includes a third metal oxide layer comprising a third metal oxide having a higher oxygen content atomic percentage than the first metal oxide, on an outer peripheral portion of the first metal oxide layer; and

wherein the second metal oxide layer is interposed between the first metal oxide layer and the third metal oxide layer, and the electrode.

16. The variable resistance non-volatile memory device according to claim 15 ,

wherein in a lower non-volatile memory element layer, an area of a portion of the third metal oxide layer and a portion of the second metal oxide layer, which portions are in contact with each other, just after formation of the corresponding non-volatile memory element layer is completed, is smaller.

17. The variable resistance non-volatile memory device according to claim 15 ,

wherein in a lower non-volatile memory element layer, an area of the upper electrode layer, just after formation of the corresponding non-volatile memory element layer is completed, is greater.

18. The variable resistance non-volatile memory device according to claim 11 ,

wherein the non-volatile memory element layer includes an oxygen barrier layer formed on a side wall of the variable resistance layer.

19. The variable resistance non-volatile memory device according to claim 11 ,

wherein the area in formation is greater in a lower non-volatile memory element layer.

20. The variable resistance non-volatile memory device according to claim 11 , being obtained by performing a step accompanied by heating, other than a deposition step and an etching step, after formation of an uppermost non-volatile memory element layer is completed.