Highly reflective coating on LED submount
View Patent ↗A submount for a light emitting stack includes a substrate and a metallization layer having circuit traces and a planar dielectric layer that fills regions between the circuit traces. The planar dielectric layer serves to minimize the amount of light lost/absorbed by the substrate and preferably reflects the internally reflected light back toward the desired light output element. To facilitate efficient manufacture, a dielectric paste is applied over the metallized layer, then planed to expose at least portions of the metal conductors for the subsequent coupling to the light emitting stack. Pedestal elements are preferably provided at select locations on the circuit traces to facilitate this coupling while allowing the remainder of the circuit traces to be covered with the dielectric layer.
1. A method comprising:
providing a plurality of conductive traces on a metallization layer above a substrate,
applying a dielectric layer above and between the conductive traces, substantially covering an entire area of the metallization layer above the substrate with the dielectric layer,
removing a portion of the dielectric layer to facilitate electrical coupling to the plurality of conductive traces, and
providing a light emitting element above the metallization layer, the conductive traces being electrically coupled to the light emitting element,
wherein the conductive traces include pedestal elements that are exposed by the removing of the portion of the dielectric layer.
2. The method of claim 1 , wherein removing the portion of the dielectric layer includes a planing operation.
3. The method of claim 1 , including providing a wavelength conversion element above the light emitting element that is configured to convert at least a portion of light of a first wavelength from the light emitting element to light of a second wavelength.
4. The method of claim 1 , wherein the conductive traces beyond the pedestal elements are not exposed by the removing of the portion of the dielectric layer.
5. The method of claim 1 , wherein the dielectric layer includes at least one of a ceramic and semiconductor.
6. The method of claim 1 , wherein the dielectric layer includes at least one of a ceramic and semiconductor within a host silicate network.
7. The method of claim 1 , wherein the dielectric layer includes at least one of a ceramic and semiconductor within one of an epoxy, silicone, and sol-gel resin.
8. The method of claim 1 , wherein the dielectric layer includes particle elements in a matrix, wherein reflectivity is provided via an index contrast between the particle elements and the matrix.
9. The method of claim 1 , including plating of at least a portion of the conductive traces.
10. The method of claim 1 , wherein the dielectric layer is reflective and substantially covers an entirety of surface area of the substrate.
11. A method comprising:
providing a plurality of conductive traces on a metallization layer above a substrate,
applying a dielectric layer above and between the conductive traces,
removing a portion of the dielectric layer to facilitate electrical coupling to the plurality of conductive traces,
providing a light emitting element above the metallization layer, the conductive traces being electrically coupled to the light emitting device
providing removable elements at select locations on the circuit traces before applying the dielectric layer above the removable elements, wherein the removing of the portion of the dielectric is configure to expose the removable elements, and
removing the removable elements to facilitate the electrical coupling to the plurality of conductive traces.
12. The method of claim 11 , wherein the conductive traces beyond the removable elements are not exposed by the removing of the removable elements.
13. A light emitting device comprising:
a submount that includes a substrate and a metallization layer that includes circuit traces and a planar dielectric layer that fills regions between the circuit traces and substantially covers an entire area of the metallization layer except for contacts to the circuit traces, and
a multi-layer stack upon the submount, the stack including a light emitting element that is coupled to the metallization layer via the contacts
wherein the circuit traces include pedestal elements that extend above a plane formed by the circuit traces beyond the pedestal elements, the dielectric layer being substantially coplanar with an upper surface of the pedestal elements.
14. The device of claim 13 , wherein the dielectric layer covers a substantial portion of the circuit traces.
15. The device of claim 13 , wherein the dielectric layer is reflective and substantially covers an entirety of surface area of the submount.
16. The device of claim 13 , including a wavelength conversion element above the light emitting element that is configured to convert light of a first wavelength emitted by the light emitting element into light of a second wavelength.
17. The device of claim 13 , wherein the dielectric layer includes at least one of a ceramic and semiconductor.
18. The device of claim 13 , wherein the dielectric layer includes at least one of a ceramic and semiconductor within a host silicate network.
19. The device of claim 13 , wherein the dielectric layer includes at least one of a ceramic and semiconductor within one of an epoxy, silicone, and sol-gel resin.
20. The device of claim 13 , wherein the dielectric includes particle elements in a matrix, wherein reflectivity is provided via an index contrast between the particle elements and the matrix.
21. The device of claim 13 , wherein at least a portion of the conductive traces are plated with at least one of nickel and gold.