IP Library › Granted Patent US 9,106,263
Granted Patent B2
US 9,106,263 · App. 13/883,118 · Granted Aug 11, 2015

Data processing device and data processing method

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Quick Facts
Patent No.
US 9,106,263
App. No.
13/883,118
Granted
Aug 11, 2015
Kind
B2
Abstract

Data processing devices and data process methods that can increase tolerance for data errors. An LDPC encoder performs encoding with an LDPC code having the code length of 16200 bits and one of the six code rates of 1/5, 1/3, 2/5, 4/9, 3/5, and 2/3. The parity check matrix H of the LDPC code is formed by arranging the elements “1” of an information matrix in the column direction in 360-column cycles, the information matrix corresponding to the information length of the parity check matrix H, the information length corresponding to the code length and the code rate, the information matrix being defined by a check matrix initial value table that shows the positions of the elements “1” of the information matrix at intervals of 360 columns. The check matrix initial value table is designed for digital broadcasting intended for portable terminals, for example. The present invention can be applied to cases where LDPC encoding and LDPC decoding are performed.

Claims (521)

1. A data processing device comprising

processing circuitry configured to perform encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 1/5,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

188 518 775 1694 1820 3394 3986 4140 4224 5236 5783

6313 6371 6792 7067 7084 7173 7445 7549 7973 9043 9219

9942 10111 10258 10300 10353 10707 10769 10796 11079

11661 12025 12042 12702 12838

7 25 392 557 625 838 1377 2223 2396 3058 3335 3348

3363 3918 4040 4128 4899 5189 5474 5838 6040 6124 7777

8220 8783 9299 9785 10924 11083 11902 12381 12513 12758

12834 12871 12950

76 4691 7180 7325 11292

6454 8048 12058 12946

3953 4932 10808 12700

4605 9117 9921 10662

2984 8202 10670 12877

4357 6205 7370 10403

5559 9847 10911 11147.

2. A data processing device comprising

processing circuitry configured to perform encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 1/3,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

77 182 354 816 916 958 1055 1261 1553 1874 2211

2490 2999 3267 3975 5018 5952 6198 6343 7027 7045 7751

7923 8649 9010 9022 9380 9956 10204 10339

5 612 1724 1737 1911 1914 2108 2496 2809 4037 5838

6950 8049 8081 9480 9512 9724 9745 9952 10203 10207 10270

10463 10486 10499 10515 10663 10678 10706 10741

22 345 1938 3636 4016 5293 6424 6589 7426 7547 8102

9038 9095 9127 9174 9239 9279 9810 10347 10403 10408

10591 10610 10632 10660 10721 10754 10765 10773 10791 17

3435 7278 9952

1442 2518 3132 7541

5464 9226 10615 10658

426 2473 8459 10750

1862 2111 6236 10546

1010 9922 10591 10735

29 2663 6553 10749

5652 7265 7789 10708

4534 5497 10784

345 3027 10761

2823 4127 10668

84 4800 9068.

3. A data processing device comprising

processing circuitry configured to perform encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 2/5,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

13 88 136 188 398 794 855 918 954 1950 2762 2837

2847 4209 4342 5092 5334 5498 5731 5837 6150 6942 7127

7402 7936 8235 8307 8600 9001 9419 9442 9710

619 792 1002 1148 1528 1533 1925 2207 2766 3021

3267 3593 3947 4832 4873 5109 5488 5882 6079 6097 6276

6499 6584 6738 6795 7550 7723 7786 8732 9060 9270 9401

499 717 1551 1791 2535 3135 3582 3813 4047 4309 5126 5186

5219 5716 5977 6236 6406 6586 6591 7085 7199 7485 7726

7878 8027 8066 8425 8802 9309 9464 9553 9671 658 4058

7824 8512

3245 4743 8117 9369

465 6559 8112 9461

975 2368 4444 6095

4128 5993 9182 9473

9 3822 5306 5320

4 8311 9571 9669

13 8122 8949 9656

3353 4449 5829 8053

7885 9118 9674

7575 9591 9670

431 8123 9271

4228 7587 9270

8847 9146 9556

11 5213 7763.

4. A data processing device comprising

processing circuitry configured to perform encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 4/9,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

567 1111 1821 2216 2255 2806 2860 3463 3697 3744

3839 3951 4212 4475 4884 5157 5679 6498 7043 7340 7403

7827 8233 8470 8699

18 24 1578 2569 3538 3714 4879 4922 5825 6417 7090

7285 7291 7451 7545 7758 7857 8180 8511 8687 8834 8877

8896 8923 8956

168 1839 1944 2745 2815 3874 4427 5366 6331 6396

6503 6512 7107 7608 7663 7742 8101 8223 8710 8722 8804

8825 8861 8909 8980

1 12 395 1035 1675 1946 2788 2823 3899 4097 4382

4741 4933 5267 7094 7503 7555 7929 8136 8377 8434 8668

8739 8756 8990

2635 4688 6722 6823

11 527 7081 7698

3930 4520 5817 7864

16 657 2009 8233

2965 5337 6600

521 6304 8963

1218 3326 6124

19 5853 8813

7129 8899 8962

3467 3632 8651

5895 6516 8973

2759 3422 8965

7205 8708 8961

4928 6921 8994

364 7206 8927

3918 4050 8435.

5. A data processing device comprising

processing circuitry configured to perform encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 3/5,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

41 588 1367 1831 1964 3424 3732 4590 4677 5455 5542

5627 6415

904 1706 2800 3732 3783 4217 4507 4999 6010 6218

6282 6363 6456

356 1871 2216 2629 2994 3719 5194 5585 6012 6273

6393 6457 6474

1676 2419 2604 3939 4186 5080 5400 5552 5971 6023

6324 6442 6445

3 770 2770 3457 3815 4253 4512 4671 5390 5393 5818

5978 6441

491 548 1033 1042 1187 3816 4378 4956 5049 5649

5684 6177 6475

1489 2817 3377 3716 4229 4512 4664 5065 5257 5477

5550 5950 6447

1546 2444 4684

15 3546 6220

1427 6199 6430

103 3629 5526

1330 6150 6255

363 5660 6422

4069 5586 5885

722 820 2823

204 2820 6181

3710 6077 6106

2655 5428 6264

1850 5989 6245

2701 5315 6477

1286 4462 6159

3356 4359 4805

13 4416 4800

3103 4357 4685

1163 5127 6435

164 3202 3934

36 230 3514.

6. A data processing device comprising

processing circuitry configured to perform encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 2/3,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

76 545 1005 1029 1390 1970 2525 2971 3448 3845 4088

4114 4163 4373 4640 4705 4970 5094

14 463 600 1676 2239 2319 2326 2815 2887 4278 4457

4493 4597 4918 4989 5038 5261 5384

451 632 829 1006 1530 1723 2205 2587 2801 3041 3849

4382 4595 4727 5006 5156 5224 5286

211 265 1293 1777 1926 2214 2909 2957 3178 3278

3771 4547 4563 4737 4879 5068 5232 5344

6 2901 3925 5384

2858 4152 5006 5202

9 1232 2063 2768

7 11 2781 3871

12 2161 2820 4078

3 3510 4668 5323

253 411 3215 5241

3919 4789 5040 5302

12 5113 5256 5352

9 1461 4004 5241

1688 3585 4480 5394

8 2127 3469 4360

2827 4049 5084 5379

1770 3331 5315 5386

1885 2817 4900 5088

2568 3854 4660

1604 3565 5373

2317 4636 5156

2480 2816 4094

14 4518 4826

127 1192 3872

93 2282 3663

2962 5085 5314

2078 4277 5089

9 5280 5292

50 2847 4742.

7. A data processing method comprising

performing, by processing circuitry, encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 1/5,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

188 518 775 1694 1820 3394 3986 4140 4224 5236 5783

6313 6371 6792 7067 7084 7173 7445 7549 7973 9043 9219

9942 10111 10258 10300 10353 10707 10769 10796 11079

11661 12025 12042 12702 12838

7 25 392 557 625 838 1377 2223 2396 3058 3335 3348

3363 3918 4040 4128 4899 5189 5474 5838 6040 6124 7777

8220 8783 9299 9785 10924 11083 11902 12381 12513 12758

12834 12871 12950

76 4691 7180 7325 11292

6454 8048 12058 12946

3953 4932 10808 12700

4605 9117 9921 10662

2984 8202 10670 12877

4357 6205 7370 10403

5559 9847 10911 11147.

8. A data processing method comprising

performing, by processing circuitry, encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 1/3,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

77 182 354 816 916 958 1055 1261 1553 1874 2211

2490 2999 3267 3975 5018 5952 6198 6343 7027 7045 7751

7923 8649 9010 9022 9380 9956 10204 10339

5 612 1724 1737 1911 1914 2108 2496 2809 4037 5838

6950 8049 8081 9480 9512 9724 9745 9952 10203 10207 10270

10463 10486 10499 10515 10663 10678 10706 10741

22 345 1938 3636 4016 5293 6424 6589 7426 7547 8102

9038 9095 9127 9174 9239 9279 9810 10347 10403 10408

10591 10610 10632 10660 10721 10754 10765 10773 10791 17

3435 7278 9952

1442 2518 3132 7541

5464 9226 10615 10658

426 2473 8459 10750

1862 2111 6236 10546

1010 9922 10591 10735

29 2663 6553 10749

5652 7265 7789 10708

4534 5497 10784

345 3027 10761

2823 4127 10668

84 4800 9068.

9. A data processing method comprising

performing, by processing circuitry, encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 2/5,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

13 88 136 188 398 794 855 918 954 1950 2762 2837

2847 4209 4342 5092 5334 5498 5731 5837 6150 6942 7127

7402 7936 8235 8307 8600 9001 9419 9442 9710

619 792 1002 1148 1528 1533 1925 2207 2766 3021

3267 3593 3947 4832 4873 5109 5488 5882 6079 6097 6276

6499 6584 6738 6795 7550 7723 7786 8732 9060 9270 9401

499 717 1551 1791 2535 3135 3582 3813 4047 4309 5126 5186

5219 5716 5977 6236 6406 6586 6591 7085 7199 7485 7726

7878 8027 8066 8425 8802 9309 9464 9553 9671 658 4058

7824 8512

3245 4743 8117 9369

465 6559 8112 9461

975 2368 4444 6095

4128 5993 9182 9473

9 3822 5306 5320

4 8311 9571 9669

13 8122 8949 9656

3353 4449 5829 8053

7885 9118 9674

7575 9591 9670

431 8123 9271

4228 7587 9270

8847 9146 9556

11 5213 7763.

10. A data processing method comprising

performing, by processing circuitry, encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 4/9,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

567 1111 1821 2216 2255 2806 2860 3463 3697 3744

3839 3951 4212 4475 4884 5157 5679 6498 7043 7340 7403

7827 8233 8470 8699

18 24 1578 2569 3538 3714 4879 4922 5825 6417 7090

7285 7291 7451 7545 7758 7857 8180 8511 8687 8834 8877

8896 8923 8956

168 1839 1944 2745 2815 3874 4427 5366 6331 6396

6503 6512 7107 7608 7663 7742 8101 8223 8710 8722 8804

8825 8861 8909 8980

1 12 395 1035 1675 1946 2788 2823 3899 4097 4382

4741 4933 5267 7094 7503 7555 7929 8136 8377 8434 8668

8739 8756 8990

2635 4688 6722 6823

11 527 7081 7698

3930 4520 5817 7864

16 657 2009 8233

2965 5337 6600

521 6304 8963

1218 3326 6124

19 5853 8813

7129 8899 8962

3467 3632 8651

5895 6516 8973

2759 3422 8965

7205 8708 8961

4928 6921 8994

364 7206 8927 3918 4050 8435.

11. A data processing method comprising

performing, by processing circuitry, encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 3/5,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

41 588 1367 1831 1964 3424 3732 4590 4677 5455 5542

5627 6415

904 1706 2800 3732 3783 4217 4507 4999 6010 6218

6282 6363 6456

356 1871 2216 2629 2994 3719 5194 5585 6012 6273

6393 6457 6474

1676 2419 2604 3939 4186 5080 5400 5552 5971 6023

6324 6442 6445

3 770 2770 3457 3815 4253 4512 4671 5390 5393 5818

5978 6441

491 548 1033 1042 1187 3816 4378 4956 5049 5649

5684 6177 6475

1489 2817 3377 3716 4229 4512 4664 5065 5257 5477

5550 5950 6447

1546 2444 4684

15 3546 6220

1427 6199 6430

103 3629 5526

1330 6150 6255

363 5660 6422

4069 5586 5885

722 820 2823

204 2820 6181

3710 6077 6106

2655 5428 6264

1850 5989 6245

2701 5315 6477

1286 4462 6159

3356 4359 4805

13 4416 4800

3103 4357 4685

1163 5127 6435

164 3202 3934

36 230 3514.

12. A data processing method comprising

performing, by processing circuitry, encoding with an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 2/3,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

76 545 1005 1029 1390 1970 2525 2971 3448 3845 4088

4114 4163 4373 4640 4705 4970 5094

14 463 600 1676 2239 2319 2326 2815 2887 4278 4457

4493 4597 4918 4989 5038 5261 5384

451 632 829 1006 1530 1723 2205 2587 2801 3041 3849

4382 4595 4727 5006 5156 5224 5286

211 265 1293 1777 1926 2214 2909 2957 3178 3278

3771 4547 4563 4737 4879 5068 5232 5344

6 2901 3925 5384

2858 4152 5006 5202

9 1232 2063 2768

7 11 2781 3871

12 2161 2820 4078

3 3510 4668 5323

253 411 3215 5241

3919 4789 5040 5302

12 5113 5256 5352

9 1461 4004 5241

1688 3585 4480 5394

8 2127 3469 4360

2827 4049 5084 5379

1770 3331 5315 5386

1885 2817 4900 5088

2568 3854 4660

1604 3565 5373

2317 4636 5156

2480 2816 4094

14 4518 4826

127 1192 3872

93 2282 3663

2962 5085 5314

2078 4277 5089

9 5280 5292

50 2847 4742.

13. A data processing device comprising

processing circuitry configured to perform decoding of an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 1/5,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

188 518 775 1694 1820 3394 3986 4140 4224 5236 5783

6313 6371 6792 7067 7084 7173 7445 7549 7973 9043 9219

9942 10111 10258 10300 10353 10707 10769 10796 11079

11661 12025 12042 12702 12838

7 25 392 557 625 838 1377 2223 2396 3058 3335 3348

3363 3918 4040 4128 4899 5189 5474 5838 6040 6124 7777

8220 8783 9299 9785 10924 11083 11902 12381 12513 12758

12834 12871 12950

76 4691 7180 7325 11292

6454 8048 12058 12946

3953 4932 10808 12700

4605 9117 9921 10662

2984 8202 10670 12877

4357 6205 7370 10403

5559 9847 10911 11147.

14. A data processing device comprising

processing circuitry configured to perform decoding of an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 1/3,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

77 182 354 816 916 958 1055 1261 1553 1874 2211

2490 2999 3267 3975 5018 5952 6198 6343 7027 7045 7751

7923 8649 9010 9022 9380 9956 10204 10339

5 612 1724 1737 1911 1914 2108 2496 2809 4037 5838

6950 8049 8081 9480 9512 9724 9745 9952 10203 10207 10270

10463 10486 10499 10515 10663 10678 10706 10741

22 345 1938 3636 4016 5293 6424 6589 7426 7547 8102

9038 9095 9127 9174 9239 9279 9810 10347 10403 10408

10591 10610 10632 10660 10721 10754 10765 10773 10791 17

3435 7278 9952

1442 2518 3132 7541

5464 9226 10615 10658

426 2473 8459 10750

1862 2111 6236 10546

1010 9922 10591 10735

29 2663 6553 10749

5652 7265 7789 10708

4534 5497 10784

345 3027 10761

2823 4127 10668

84 4800 9068.

15. A data processing device comprising

processing circuitry configured to perform decoding of an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 2/5,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

13 88 136 188 398 794 855 918 954 1950 2762 2837

2847 4209 4342 5092 5334 5498 5731 5837 6150 6942 7127

7402 7936 8235 8307 8600 9001 9419 9442 9710

619 792 1002 1148 1528 1533 1925 2207 2766 3021

3267 3593 3947 4832 4873 5109 5488 5882 6079 6097 6276

6499 6584 6738 6795 7550 7723 7786 8732 9060 9270 9401

499 717 1551 1791 2535 3135 3582 3813 4047 4309 5126 5186

5219 5716 5977 6236 6406 6586 6591 7085 7199 7485 7726

7878 8027 8066 8425 8802 9309 9464 9553 9671 658 4058

7824 8512

3245 4743 8117 9369

465 6559 8112 9461

975 2368 4444 6095

4128 5993 9182 9473

9 3822 5306 5320

4 8311 9571 9669

13 8122 8949 9656

3353 4449 5829 8053

7885 9118 9674

7575 9591 9670

431 8123 9271

4228 7587 9270

8847 9146 9556

11 5213 7763.

16. A data processing device comprising

processing circuitry configured to perform decoding of an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 4/9,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

567 1111 1821 2216 2255 2806 2860 3463 3697 3744

3839 3951 4212 4475 4884 5157 5679 6498 7043 7340 7403

7827 8233 8470 8699

18 24 1578 2569 3538 3714 4879 4922 5825 6417 7090

7285 7291 7451 7545 7758 7857 8180 8511 8687 8834 8877

8896 8923 8956

168 1839 1944 2745 2815 3874 4427 5366 6331 6396

6503 6512 7107 7608 7663 7742 8101 8223 8710 8722 8804

8825 8861 8909 8980

1 12 395 1035 1675 1946 2788 2823 3899 4097 4382

4741 4933 5267 7094 7503 7555 7929 8136 8377 8434 8668

8739 8756 8990

2635 4688 6722 6823

11 527 7081 7698

3930 4520 5817 7864

16 657 2009 8233

2965 5337 6600

521 6304 8963

1218 3326 6124

19 5853 8813

7129 8899 8962

3467 3632 8651

5895 6516 8973

2759 3422 8965

7205 8708 8961

4928 6921 8994

364 7206 8927

3918 4050 8435.

17. A data processing device comprising

processing circuitry configured to perform decoding of an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 3/5,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

41 588 1367 1831 1964 3424 3732 4590 4677 5455 5542

5627 6415

904 1706 2800 3732 3783 4217 4507 4999 6010 6218

6282 6363 6456

356 1871 2216 2629 2994 3719 5194 5585 6012 6273

6393 6457 6474

1676 2419 2604 3939 4186 5080 5400 5552 5971 6023

6324 6442 6445

3 770 2770 3457 3815 4253 4512 4671 5390 5393 5818

5978 6441

491 548 1033 1042 1187 3816 4378 4956 5049 5649

5684 6177 6475

1489 2817 3377 3716 4229 4512 4664 5065 5257 5477

5550 5950 6447

1546 2444 4684

15 3546 6220

1427 6199 6430

103 3629 5526

1330 6150 6255

363 5660 6422

4069 5586 5885

722 820 2823

204 2820 6181

3710 6077 6106

2655 5428 6264

1850 5989 6245

2701 5315 6477

1286 4462 6159

3356 4359 4805

13 4416 4800

3103 4357 4685

1163 5127 6435

164 3202 3934

36 230 3514.

18. A data processing device comprising

processing circuitry configured to perform decoding of an LDPC (Low Density Parity Check) code having a code length of 16200 bits and a code rate of 2/3,

wherein a parity check matrix of the LDPC code is formed by arranging elements “1” of an information matrix in a column direction in 360-column cycles, the information matrix being defined by a check matrix initial value table showing positions of the elements “1” of the information matrix at intervals of 360 columns, the information matrix corresponding to an information length of the parity check matrix, the information length corresponding to the code length and the code rate, the check matrix initial value table being formed with:

76 545 1005 1029 1390 1970 2525 2971 3448 3845 4088

4114 4163 4373 4640 4705 4970 5094

14 463 600 1676 2239 2319 2326 2815 2887 4278 4457

4493 4597 4918 4989 5038 5261 5384

451 632 829 1006 1530 1723 2205 2587 2801 3041 3849

4382 4595 4727 5006 5156 5224 5286

211 265 1293 1777 1926 2214 2909 2957 3178 3278

3771 4547 4563 4737 4879 5068 5232 5344

6 2901 3925 5384

2858 4152 5006 5202

9 1232 2063 2768

7 11 2781 3871

12 2161 2820 4078

3 3510 4668 5323

253 411 3215 5241

3919 4789 5040 5302

12 5113 5256 5352

9 1461 4004 5241

1688 3585 4480 5394

8 2127 3469 4360

2827 4049 5084 5379

1770 3331 5315 5386

1885 2817 4900 5088

2568 3854 4660

1604 3565 5373

2317 4636 5156

2480 2816 4094

14 4518 4826

127 1192 3872

93 2282 3663

2962 5085 5314

2078 4277 5089

9 5280 5292

50 2847 4742.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2017
From: SONY CORPORATION
To: SATURN LICENSING LLC
Reel/Frame 043177/0794 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2013
From: YAMAMOTO, MAKIKO; SHINOHARA, YUJI
To: SONY CORPORATION
Reel/Frame 030337/0204 →