Data processing device and data processing method
View Patent ↗A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example.
1. A data processing device for processing control data prior to aggregation of said control data with payload data in a data frame for transmission, comprising:
circuitry configured to
pad control data directly with dummy data, the control data being necessary for demodulation;
scramble post-padding control data, the post-padding control data being the padded control data;
generate replacement data by replacing scrambled dummy data in the scrambled post-padding control data with the dummy data; and
perform error correction encoding on the replacement data.
2. The data processing device according to claim 1 , wherein the circuitry is configured to
determine a parity bit for data to be subjected to the error correction encoding, and add the parity bit to the data to be subjected to the error correction encoding, to obtain an error correcting code, and
perform shortening by deleting the dummy data from the error correcting code and puncturing a parity bit of the error correcting code.
3. The data processing device according to claim 1 , wherein the circuitry performs the padding with the dummy data, to adjust a data length of padded data to a target data length of the error correction encoding.
4. The data processing device according to claim 1 ,
wherein the circuitry includes:
a register group formed with fifteen registers connected in series, a register in a later stage latching bits latched by a register in a previous stage;
a first EXOR circuit that calculates an exclusive OR between bits latched by a fourteenth register and bits latched by a fifteenth register; and
a second EXOR circuit that calculates an exclusive OR between an output of the first EXOR circuit and data to be scrambled, and outputs a result of the calculation as scrambled data,
wherein a first register of the register group latches the output of the first EXOR circuit, and
wherein bits 1 , 0 , 0 , 1 , 0 , 1 , 0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , and 0 are set as initial values in the first through fifteenth registers of the register group, respectively.
5. The data processing device according to claim 1 , wherein the control data is one of:
first data necessary for demodulating payload data;
second data necessary for demodulating the first data; and
the first and second data.
6. The data processing device according to claim 1 , wherein a new frame containing an error correcting code obtained through the error correction encoding is multiplexed with a T2 frame specified in DVB-T.2 and is transmitted.
7. The data processing device according to claim 1 , wherein
a preamble is placed at the top of each of a T2 frame and a new frame,
the preamble of the T2 frame contains information identifying the T2 frame, and
the preamble of the new frame contains information identifying the new frame.
8. A data processing device comprising:
circuitry configured to
scramble control data necessary for demodulation;
pad the scrambled control data directly with dummy data; and
perform error correction encoding on post-padding scrambled data formed by padding the scrambled control data with the dummy data.
9. A data processing method for processing control data prior to aggregation of said control data with payload data in a data frame for transmission, the method comprising:
padding control data directly with dummy data, the control data being necessary for demodulation;
scrambling post-padding control data, the post-padding control data being the padded control data;
generating replacement data by replacing scrambled dummy data in the scrambled post-padding control data with the dummy data; and
performing error correction encoding on the replacement data.
10. A data processing method comprising:
scrambling control data necessary for demodulation;
padding the scrambled control data directly with dummy data; and
performing error correction encoding on post-padding scrambled data formed by padding the scrambled control data with the dummy data.
11. A data processing device comprising:
circuitry configured to
perform error correction to decode an error correcting code in replacement data, the error correcting code being obtained by a transmission device; and
descramble the replacement data,
wherein the transmission device having
padded control data necessary for demodulation directly with dummy data,
scrambled post-padding control data that is the padded control data,
generated the replacement data by replacing scrambled dummy data in the scrambled post-padding control data with the dummy data, and
performed error correction encoding on the replacement data to provide in the replacement data the error correcting code.
12. The data processing device according to claim 11 ,
wherein the transmission device having performed shortening by deleting the dummy data from the error correcting code obtained through the error correction encoding and puncturing a parity bit of the error correcting code, and
wherein the circuitry is configured to
restore a pre-shortening error correcting code by padding the post-shortening error correcting code obtained by the transmission device with the dummy data, and depuncture the parity bit.
13. The data processing device according to claim 12 , wherein the circuitry performs the padding with the dummy data to adjust a data length of padded data to a target data length of the error correction encoding.
14. The data processing device according to claim 12 ,
wherein the circuitry includes:
a register group formed with fifteen registers connected in series, a register in a later stage latching bits latched by a register in a previous stage;
a first EXOR circuit that calculates an exclusive OR between bits latched by a fourteenth register and bits latched by a fifteenth register; and
a second EXOR circuit that calculates an exclusive OR between an output of the first EXOR circuit and data to be scrambled, and outputs a result of the calculation as scrambled data,
wherein a first register of the register group latches the output of the first EXOR circuit, and
wherein bits 1 , 0 , 0 , 1 , 0 , 1 , 0 , 1 , 0 , 0 , 0 , 0 , 0 , 0 , and 0 are set as initial values in the first through fifteenth registers of the register group, respectively.
15. The data processing device according to claim 12 , wherein a new frame containing the error correcting code obtained through the error correction encoding is multiplexed with a T2 frame specified in DVB-T.2 and is transmitted.
16. The data processing device according to claim 11 , wherein the circuitry is configured to
delete descrambled dummy data from the descrambled replacement data.
17. The data processing device according to claim 12 , wherein the control data is one of:
first data necessary for demodulating payload data;
second data necessary for demodulating the first data; and
the first and second data.
18. The data processing device according to claim 12 , wherein
a preamble is placed at the top of each of a T2 frame and a new frame,
the preamble of the T2 frame contains information identifying the T2 frame, and
the preamble of the new frame contains information identifying the new frame.
19. A data processing device comprising:
circuitry configured to
perform error correction to decode an error correcting code in post-padding scrambled data, the error correcting code being obtained by a transmission device;
delete dummy data from the post-padding scrambled data, and output scrambled control data; and
descramble the scrambled control data,
wherein the transmission device having
scrambled control data necessary for demodulation,
padded the scrambled control data directly with the dummy data, and
performed error correction encoding on the post-padding scrambled data formed by padding the scrambled control data with the dummy data and to provide in the post-padded scrambled data the error correcting code.
20. A data processing method comprising:
performing error correction to decode an error correcting code in replacement data, the error correcting code being obtained by a transmission device; and
descrambling the replacement data,
wherein the transmission device having
padded control data necessary for demodulation directly with dummy data,
scrambled post-padding control data that is the padded control data,
generated the replacement data by replacing scrambled dummy data in the scrambled post-padding control data with the dummy data, and
performed error correction encoding on the replacement data to provide in the replacement data the error correcting code.
21. A data processing method comprising:
performing error correction to decode an error correcting code in post-padding scrambled data, the error correcting code being obtained by a transmission device;
deleting dummy data from the post-padding scrambled data, to output scrambled control data; and
descrambling the scrambled control data,
wherein the transmission device having
scrambled control data necessary for demodulation,
padded the scrambled control data directly with the dummy data, and
performed error correction encoding on the post-padding scrambled data formed by padding the scrambled control data with the dummy data and to provide in the post-padded scrambled data the error correcting code.