Systems and methods for preventing adjacent track erasure
A data processing circuit includes a subtraction circuit operable to subtract an ideal version of a data pattern from a sampled version of a data pattern to yield a difference signal, an error calculation circuit operable to calculate an error between the ideal version of the data pattern and the sampled version of the data pattern based on the difference signal, and a comparator circuit operable to compare the error with a threshold value and operable to assert a track refresh signal if the error is greater than the threshold value. The track refresh signal is operable to trigger a magnetic storage device to refresh data on a data track.
1. A data processing circuit comprising:
a subtraction circuit operable to subtract an ideal version of a data pattern from a sampled version of the data pattern to yield a difference signal;
an error calculation circuit operable to calculate an error between the ideal version of the data pattern and the sampled version of the data pattern based on the difference signal; and
a comparator circuit operable to compare the error with a threshold value and operable to assert a track refresh signal if the error is greater than the threshold value, wherein the track refresh signal is operable to trigger a magnetic storage device to refresh data on a data track.
2. The data processing circuit of claim 1 , wherein the data processing circuit is operable to analyze the data track on a storage medium with the comparator circuit when an adjacent track to the data track is written.
3. The data processing circuit of claim 2 , further comprising a track write counter for each of a plurality of data tracks on the storage medium, wherein the track write counters are incremented each time a corresponding one of the plurality if data tracks are written.
4. The data processing circuit of claim 2 , wherein the data processing circuit is operable to trigger the analyzing based in part on a number of times the data track has been written since the adjacent track was last written.
5. The data processing circuit of claim 1 , wherein the data processing circuit is operable to refresh the data track when an adjacent data track is written to reduce adjacent track erasure when the error is greater than the threshold value.
6. The data processing circuit of claim 1 , further comprising a pattern selection circuit operable to obtain the sampled version of the data pattern and the ideal version of the data pattern from a sampled data stream and an ideal data stream.
7. The data processing circuit of claim 6 , wherein the pattern selection circuit is operable to select a number of bits from each group of bits in the sampled data stream and the ideal data stream.
8. The data processing circuit of claim 1 , wherein the threshold value is programmable.
9. The data processing circuit of claim 1 , wherein the error calculation circuit comprises a mean squared error calculation circuit.
10. The data processing circuit of claim 1 , further comprising a saturation circuit operable to limit the difference signal to a predetermined value.
11. The data processing circuit of claim 1 , further comprising an analog to digital converter operable to generate the sampled version of the data pattern from an analog input.
12. The data processing circuit of claim 11 , wherein the sampled version of the data pattern comprises X samples from the analog to digital converter.
13. The data processing circuit of claim 11 , further comprising a digital finite impulse response filter operable to equalize an output of the analog to digital converter, wherein the sampled version of the data pattern comprises an output of the digital finite impulse response filter, and wherein the sampled version of the data pattern comprises an output of the digital finite impulse response filter comprises Y samples.
14. The data processing circuit of claim 1 , wherein the circuit is implemented as an integrated circuit.
15. A method for preventing adjacent track erasure, comprising:
based on a write operation to an adjacent data track on a storage medium, performing a track erasure prevention operation comprising:
obtaining a data pattern from a data track;
calculating an ideal value for the data pattern;
calculating an error value between the data pattern and the ideal value for the data pattern;
comparing the error value with a threshold; and
refreshing the data track when the error value is greater than the threshold, wherein the track erasure prevention operation is triggered when a count of write operations to the adjacent data track exceeds a threshold.
16. The method of claim 15 , wherein calculating the error value comprises calculating a mean squared error between the data pattern and the ideal value for the data pattern.
17. The method of claim 15 , wherein calculating the ideal value for the data pattern comprises calculating a hard decision for the data pattern and performing a convolution operation between the hard decision and a partial response target.
18. The method of claim 15 , further comprising reading a programmable value for the threshold.
19. A storage device, comprising:
a storage medium;
a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to a data set on the storage medium; and
a read channel circuit comprising an adjacent track erasure prevention circuit, the adjacent track erasure prevention circuit comprising:
a subtraction circuit operable to subtract an ideal version of a data pattern from a sampled version of the data pattern to yield a difference signal;
an error calculation circuit operable to calculate an error between the ideal version of the data pattern and the sampled version of the data pattern based on the difference signal; and
a comparator circuit operable to compare the error with a threshold value and operable to assert a track refresh signal if the error is greater than the threshold value, wherein the track refresh signal is operable to cause the head assembly to refresh data on a data track.
20. The storage device of claim 19 , wherein the adjacent track erasure prevention circuit is operable to refresh the data on the data track when an adjacent data track is written.