IP Library Granted Patent US 9,183,142
Granted Patent B2
US 9,183,142 · App. 13/886,325 · Granted Nov 10, 2015

Reducing flash memory write amplification and latency

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Quick Facts
Patent No.
US 9,183,142
App. No.
13/886,325
Granted
Nov 10, 2015
Kind
B2
Abstract

Data is distributed to solid-state disks (SSDs) using the RAID-0 technique. Based on a utilization of a first region of a first one of the SSDs, the first region is selected for garbage collection. Valid data from the first region is copied to an active region of the first one of the SSDs as part of a process of garbage collection. While the process of garbage collection is being performed, data is distributed to a subset of the SSDs using the RAID-0 technique where the subset of the SSDs does not include the first one of the plurality of nonvolatile solid-state memories selected for garbage collection.

Claims (45)

1. A method of storing data to a nonvolatile solid-state memory, comprising:

distributing data from a host to a plurality of nonvolatile solid-state memories using a RAID-0 technique;

based on a utilization of a first region of a first one of the plurality of nonvolatile solid-state memories, selecting the first region of the first one of the plurality of nonvolatile solid-state memories for garbage collection;

copying valid data from a region of a nonvolatile random access memory to at least the first region of the first one of the plurality of nonvolatile solid-state memories as part of a process of garbage collection; and

while the process of garbage collection is being performed, distributing the data from the host to a subset of the plurality of nonvolatile solid-state memories using the RAID-0 technique, the subset of the plurality of nonvolatile solid-state memories not including the first one of the plurality of nonvolatile solid-state memories selected for garbage collection.

2. The method of claim 1 , further comprising:

after the process of garbage collection is complete on the first region of the first one of the plurality of nonvolatile solid-state memories, distributing the data from the host to the complete set of the plurality of nonvolatile solid-state memories using the RAID-0 technique.

3. The method of claim 1 , further comprising:

maintaining a first set of flags to indicate which of the plurality of nonvolatile solid-state memories is undergoing the process of garbage collection.

4. The method of claim 3 , further comprising:

maintaining a second set of flags to indicate which of the plurality of nonvolatile solid-state memories being used for garbage collection information on a respective active region of the plurality of nonvolatile solid-state memories.

5. The method of claim 4 , further comprising:

maintaining a third set of flags associated with a plurality of logical block addresses that indicate when metadata associated with each of the plurality of logical block addresses has not been written to the plurality of nonvolatile solid-state memories.

6. The method of claim 3 , further comprising:

after the process of garbage collection is complete on the first region of the first one of the plurality of nonvolatile solid-state memories, distributing the data from the host to the complete set of the plurality of nonvolatile solid-state memories using the RAID-0 technique.

7. A nonvolatile solid-state memory storage system, comprising:

a plurality of nonvolatile solid-state memories; and

a nonvolatile solid-state memory driver configured to distribute data from a host to the plurality of nonvolatile solid-state memories using a RAID-0 technique and configured to, based on a utilization of a first region of a first one of the plurality of nonvolatile solid-state memories, select the first region of the first one of the plurality of nonvolatile solid-state memories for garbage collection, and configured to copy valid data from a region of a nonvolatile random access memory to at least the first region of the first one of the plurality of nonvolatile solid-state memories as part of a process of garbage collection, and configured to, while the process of garbage collection is being performed, distribute the data from the host to a subset of the plurality of nonvolatile solid-state memories using the RAID-0 technique, the subset of the plurality of nonvolatile solid-state memories not including the first one of the plurality of nonvolatile solid-state memories selected for garbage collection.

8. The storage system of claim 7 , wherein the nonvolatile solid-state memory driver is further configured to:

after the process of garbage collection is complete on the first region of the first one of the plurality of nonvolatile solid-state memories, distribute the data from the host to the complete set of the plurality of nonvolatile solid-state memories using the RAID-0 technique.

9. The storage system of claim 7 , wherein the nonvolatile solid-state memory driver is further configured to:

maintain a first set of flags to indicate which of the plurality of nonvolatile solid-state memories is undergoing the process of garbage collection.

10. The storage system of claim 9 , wherein the nonvolatile solid-state memory driver is further configured to:

maintain a second set of flags to indicate which of the plurality of nonvolatile solid-state memories being used for garbage collection information on a respective active region of the plurality of nonvolatile solid-state memories.

11. The storage system of claim 10 , wherein the nonvolatile solid-state memory driver is further configured to:

maintain a third set of flags associated with a plurality of logical block addresses that indicate when metadata associated with each of the plurality of logical block addresses has not been written to the plurality of nonvolatile solid-state memories.

12. The storage system of claim 9 , wherein the nonvolatile solid-state memory driver is further configured to:

after the process of garbage collection is complete on the first region of the first one of the plurality of nonvolatile solid-state memories, distribute the data from the host to the complete set of the plurality of nonvolatile solid-state memories using the RAID-0 technique.

13. The storage system of claim 7 , wherein each of the plurality of nonvolatile solid-state memories are included in solid-state disks having a respective controller that is responsive to instructions received from the nonvolatile solid-state memory driver.

14. The storage system of claim 7 , wherein the plurality of nonvolatile solid-state memories and the nonvolatile random access memory are included in a host bus adapter.

15. A non-transitory computer readable medium having instructions stored thereon for storing data to a nonvolatile solid-state memory that, when executed by a computer, at least instruct the computer to:

distribute data from a host to a plurality of nonvolatile solid-state memories using a RAID-0 technique;

based on a utilization of a first region of a first one of the plurality of nonvolatile solid-state memories, select the first region of the first one of the plurality of nonvolatile solid-state memories for garbage collection;

copy valid data from the first region of the first one of the plurality of nonvolatile solid-state memories to an active region of the first one of the plurality of nonvolatile solid-state memories as part of a process of garbage collection; and

while the process of garbage collection is being performed, distribute the data from the host to a subset of the plurality of nonvolatile solid-state memories using the RAID-0 technique, the subset of the plurality of nonvolatile solid-state memories not including the first one of the plurality of nonvolatile solid-state memories selected for garbage collection.

16. The medium of claim 15 , wherein the computer is further instructed to:

after the process of garbage collection is complete on the first region of the first one of the plurality of nonvolatile solid-state memories, distribute the data from the host to the complete set of the plurality of nonvolatile solid-state memories using the RAID-0 technique.

17. The medium of claim 15 , wherein the computer is further instructed to:

maintain a first set of flags to indicate which of the plurality of nonvolatile solid-state memories is undergoing the process of garbage collection.

18. The medium of claim 17 , wherein the computer is further instructed to:

maintain a second set of flags to indicate which of the plurality of nonvolatile solid-state memories being used for garbage collection information on a respective active region of the plurality of nonvolatile solid-state memories.

19. The medium of claim 18 , wherein the computer is further instructed to:

maintaining a third set of flags associated with a plurality of logical block addresses that indicate when metadata associated with each of the plurality of logical block addresses has not been written to the plurality of nonvolatile solid-state memories.

20. The medium of claim 17 , wherein the computer is further instructed to:

after the process of garbage collection is complete on the first region of the first one of the plurality of nonvolatile solid-state memories, distribute the data from the host to the complete set of the plurality of nonvolatile solid-state memories using the RAID-0 technique.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2013
From: SHIVASHANKARAIAH, VINAY BANGALORE
To: LSI CORPORATION
Reel/Frame 030343/0924 →