Low power dual voltage mode receiver

1. A dual-voltage receiver, comprising:

a voltage detector;

a high voltage Schmitt trigger coupled to the voltage detector;

a low voltage Schmitt trigger coupled to the voltage detector; and

a combined level shifter coupled to the high voltage Schmitt trigger and the low voltage Schmitt trigger, wherein the high voltage Schmitt trigger is configured to be on and the low voltage Schmitt trigger is configured to be off when the voltage detector outputs a high voltage detect signal.

2. The dual-voltage receiver of claim 1 wherein the low voltage Schmitt trigger further comprises a non-inverting Schmitt trigger followed by an inverter.

3. The dual voltage receiver of claim 1 wherein the combined level shifter further comprises a high voltage device coupled in series with a low voltage device.

4. The dual voltage receiver of claim 1 wherein the combined level shifter further comprises a high voltage device coupled in parallel with a low voltage device.

5. The dual voltage receiver of claim 1 wherein the combined level shifter further comprises a high voltage device configured to receive a first signal from the high voltage Schmitt trigger coupled in series with a low voltage device configured to receive a second signal from the low voltage Schmitt trigger.

6. The dual voltage receiver of claim 1 wherein the combined level shifter further comprises a high voltage device configured to receive a first signal from the high voltage Schmitt trigger coupled in parallel with a low voltage device configured to receive a second signal from the low voltage Schmitt trigger.

7. A dual-voltage receiver comprising:

an electrostatic discharge and filter capacitor stage configured to receive an input voltage and a voltage detect signal and output a filtered signal;

a low voltage hysteresis inverter coupled to the electrostatic discharge and filter capacitor stage configured to receive the filtered signal;

a high voltage inverter stage coupled to the input;

an inverting low-voltage level shifter stage coupled to the low voltage hysteresis inverter; and

a combined level shifter with AND gate stage coupled to the inverting low-voltage level shifter stage and the high voltage inverter stage.

8. The dual-voltage receiver of claim 7 wherein the combined level shifter with AND gate stage further comprises a low voltage PMOS transistor coupled in parallel with a high voltage PMOS transistor.

9. The dual-voltage receiver of claim 7 wherein the combined level shifter with AND gate stage further comprises:

a low voltage PMOS transistor having a drain and a source; and

a high voltage PMOS transistor having a drain coupled to the drain of the low voltage PMOS transistor and a source coupled to the source of the low voltage PMOS transistor.

10. The dual-voltage receiver of claim 7 wherein the combined level shifter with AND gate stage further comprises:

a low voltage PMOS transistor having a drain and a source;

a high voltage PMOS transistor having a drain coupled to the drain of the low voltage PMOS transistor and a source coupled to the source of the low voltage PMOS transistor; and

a low voltage NMOS transistor having a drain coupled to the source of the low voltage PMOS transistor.

11. The dual-voltage receiver of claim 7 wherein the combined level shifter with AND gate stage further comprises:

a low voltage PMOS transistor having a drain and a source;

a high voltage PMOS transistor having a drain coupled to the drain of the low voltage PMOS transistor and a source coupled to the source of the low voltage PMOS transistor;

a low voltage NMOS transistor having a drain coupled to the source of the low voltage PMOS transistor and a source; and

a high voltage NMOS transistor having a drain coupled to the source of the low voltage NMOS transistor.

12. The dual-voltage receiver of claim 7 wherein the combined level shifter with AND gate stage further comprises:

a low voltage PMOS transistor having a drain and a source;

a high voltage PMOS transistor having a drain coupled to the drain of the low voltage PMOS transistor and a source coupled to the source of the low voltage PMOS transistor;

a low voltage NMOS transistor having a drain coupled to the source of the low voltage PMOS transistor and a source;

a first high voltage NMOS transistor having a drain coupled to the source of the low voltage NMOS transistor; and

a second high voltage NMOS transistor having a drain coupled to the source of the low voltage NMOS transistor.

13. The dual-voltage receiver of claim 11 wherein the combined level shifter with AND gate stage further comprises:

a first low voltage PMOS transistor having a drain and a source; and

a second low voltage PMOS transistor having a drain coupled to the drain of the first low voltage PMOS transistor and a gate coupled to the source of the first low voltage PMOS transistor.

14. A dual-voltage receiver, comprising:

a voltage detector;

a high voltage receiver coupled to the voltage detector;

a low voltage receiver coupled to the voltage detector; and

a level shifter comprising a high voltage device coupled to the high voltage receiver and a low voltage device coupled to the low voltage receiver, wherein the high voltage device is coupled to the low voltage device and the high voltage receiver is configured to be on and the low voltage receiver is configured to be off when the voltage detector outputs a high voltage detect signal.

15. The dual voltage receiver of claim 14 wherein the high voltage device coupled in series with the low voltage device.

16. The dual voltage receiver of claim 14 wherein the high voltage device coupled in parallel with the low voltage device.

17. The dual voltage receiver of claim 14 wherein the high voltage device is coupled in series to the low voltage device and in parallel to a second low voltage device.

18. The dual voltage receiver of claim 14 wherein the low voltage device is coupled in series to the high voltage device and in series to a second high voltage device.

19. The dual voltage receiver of claim 14 wherein the high voltage device is coupled in series to the low voltage device and the high voltage device and the low voltage device are coupled to a gate of a second low voltage device.

20. The dual voltage receiver of claim 14 wherein the high voltage device is coupled in series to the low voltage device and the high voltage device and the low voltage device are coupled to a gate of a second low voltage device and a gate of a third low voltage device.