Multi-mode power amplifier architecture
View Patent ↗Radio frequency (RF) circuitry, which includes a time division duplex (TDD)/frequency division duplex (FDD) driver stage, a TDD final stage, an FDD final stage, and power directing circuitry, is disclosed. The power directing circuitry is coupled between the TDD/FDD driver stage and the TDD final stage, and is further coupled between the TDD/FDD driver stage and the FDD final stage.
1. Radio frequency (RF) circuitry configured to selectively operate in one of a TDD operating mode and an FDD operating mode, and comprising:
an RF power splitter;
a time division duplex (TDD)/frequency division duplex (FDD) driver stage;
a TDD final stage, wherein during the TDD operating mode, the TDD final stage is configured to receive and amplify a first RF input signal from the RF power splitter to provide a first RF output signal; and
an FDD final stage comprising an in-phase stage and a quadrature-phase stage, wherein during the FDD operating mode, the in-phase stage is configured to receive and amplify an RF in-phase input signal from the RF power splitter to provide an RF in-phase output signal, and the quadrature-phase stage is configured to receive and amplify an RF quadrature-phase input signal from the RF power splitter to provide an RF quadrature-phase output signal,
wherein the RF power splitter is coupled between an output from the TDD/FDD driver stage and corresponding inputs to each of the in-phase stage, the quadrature-phase stage, and the TDD final stage.
2. The RF circuitry of claim 1 further comprising RF bypass circuitry coupled to the output from the TDD/FDD driver stage.
3. The RF circuitry of claim 2 further configured to operate in one of the TDD operating mode, the FDD operating mode, and a bypass operating mode, such that
during the bypass operating mode, the TDD/FDD driver stage is configured to provide a third RF output signal.
4. The RF circuitry of claim 3 wherein:
during the TDD operating mode, the FDD final stage is further configured to be disabled;
during the FDD operating mode, the TDD final stage is further configured to be disabled; and
during the bypass operating mode, both the TDD final stage and the FDD final stage are further configured to be disabled.
5. The RF circuitry of claim 1 wherein the TDD final stage is a single-ended stage.
6. The RF circuitry of claim 5 wherein:
the RF power splitter is a 90 degree power splitter;
an in-phase port from the 90 degree power splitter is coupled to the in-phase stage;
a quadrature-phase port from the 90 degree power splitter is coupled to the quadrature-phase stage; and
an isolated port from the 90 degree power splitter is coupled to the TDD final stage.
7. The RF circuitry of claim 1 further comprising a direct current (DC)-DC converter coupled between a DC power source and the FDD final stage.
8. The RF circuitry of claim 7 further comprising the DC power source.
9. The RF circuitry of claim 7 wherein the DC power source is a battery.
10. The RF circuitry of claim 7 wherein:
the TDD/FDD driver stage is coupled to the DC-DC converter; and
the TDD final stage is coupled to the DC power source.
11. The RF circuitry of claim 1 wherein
during both the TDD operating mode and the FDD operating mode, the TDD/FDD driver stage is configured to provide a driver stage output signal.
12. The RF circuitry of claim 11 wherein the FDD operating mode comprises a first FDD operating mode and a second FDD operating mode.
13. The RF circuitry of claim 1 wherein control circuitry is adapted to select the one of the TDD operating mode and the FDD operating mode.
14. The RF circuitry of claim 13 further comprising the control circuitry.
15. The RF circuitry of claim 1 further comprising an RF power combiner configured to during the FDD operating mode, receive and combine the RF in-phase output signal and the RF quadrature-phase output signal to provide a second RF output signal, wherein the second RF output signal is a long term evolution (LTE) RF signal.
16. The RF circuitry of claim 1 further comprising an RF power combiner configured to during the FDD operating mode, receive and combine the RF in-phase output signal and the RF quadrature-phase output signal to provide a second RF output signal, wherein the second RF output signal is a wideband code division multiple access (WCDMA) RF signal.
17. The RF circuitry of claim 1 wherein the first RF output signal is a global system for mobile communications (GSM) RF signal.
18. The RF circuitry of claim 1 wherein the first RF output signal is a long term evolution (LTE) RF signal.
19. The RF circuitry of claim 1 wherein the first RF output signal is a time division synchronous code division multiple access (TD-SCDMA) RF signal.