IP Library Granted Patent US 9,374,002
Granted Patent B2
US 9,374,002 · App. 13/889,704 · Granted Jun 21, 2016

Switch control circuit, coupled inductor boost converter including the same, and driving method of the coupled inductor boost converter

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Quick Facts
Patent No.
US 9,374,002
App. No.
13/889,704
Granted
Jun 21, 2016
Kind
B2
Abstract

The present invention related to a switch control circuit, a coupled inductor boost converter including the same, and a driving method thereof. The coupled inductor boost converter includes a first inductor connected between an input voltage and a first node, a second inductor connected between the first node and a second node, and a power switch connected between the first node and a ground, and a switch control circuit. The switch control circuit receives a voltage of the second node and turn on the power switch by using the voltage of the second node at a time when a voltage of the first node becomes a zero voltage.

Claims (35)

1. A coupled inductor boost converter comprising:

a first inductor including a first end coupled to an input voltage and a second end directly coupled to a first node;

a second inductor including a first end directly coupled to the first node and a second end;

a power switch coupled between the first node and a ground; and

a switch control circuit configured to measure a voltage at the second end of the second inductor and turn on the power switch based on the voltage of the second node when a voltage of the first node is zero voltage.

2. The coupled inductor boost converter of claim 1 , further comprising an output diode including an anode coupled to the second node and a cathode coupled to an output voltage.

3. The coupled inductor boost converter of claim 2 , wherein the switch control circuit includes a zero voltage detector configured to generate a first level on-pulse signal when the voltage of the second node reaches a zero voltage, the switch control circuit being configured to generate a gate voltage for turning on the power switch based on the first level on-pulse signal.

4. The coupled inductor boost converter of claim 3 , wherein the switch control circuit is configured to turn off the power switch based on a result of a comparison between an error voltage and a sense voltage.

5. The coupled inductor boost converter of claim 4 , wherein the switch control circuit further comprises:

an error amplifier configured to generate the error voltage by amplifying a difference between the output voltage of the coupled inductor boost converter and a predetermined reference voltage; and

a PWM controller configured to compare the error voltage with the sense voltage based on a current flowing through the power switch and generate an off signal to turn off the power switch based on the comparison result.

6. The coupled inductor boost converter of claim 5 , wherein the switch control circuit further comprises an SR flip-flop configured to generate the gate voltage to turn on the power switch based on the on-pulse signal and a gate voltage to turn off the power switch based on an off-pulse signal.

7. The coupled inductor boost converter of claim 1 , further comprising a clamp configured to receive and clamp a voltage of the second node to a first clamping voltage when the voltage of the second node is higher than a first clamping reference voltage, the clamp being further configured to clamp the voltage of the second node to a second clamping voltage when the voltage of the second node is lower than a second clamping reference voltage.

8. A method of driving a coupled inductor boost converter, said method comprising:

providing a coupled inductor boost converter, said coupled inductor boost converter comprising:

a first inductor including a first end coupled to an input voltage and a second end directly coupled to a first node,

a second inductor including a first end directly coupled to the first node and a second end, and

a power switch connected to the first node;

detecting a time when a voltage measured at the second end of the second inductor becomes a zero voltage; and

turning on the power switch at the detected zero voltage time.

9. The method of claim 8 , wherein turning on the power switch comprises:

generating an on-pulse signal at the detected zero voltage time; and

generating a gate voltage to turn on the power switch based on the on-pulse signal.

10. The method of claim 8 , further comprising:

generating an error voltage by amplifying a difference between an output voltage of the coupled inductor boost converter and a predetermined reference voltage; and

turning off the power switch based on a comparison between the error voltage and a sense voltage based on a current flowing through the power switch.

11. A switch control circuit for controlling a switching operation of a power switch coupled directly to a first node, the first node coupled directly to a second end of a first inductor and to a first end of a second inductor, the first inductor and the second inductor coupled to an output voltage through an output diode, said switch control circuit comprising:

a zero voltage detector configured to generate an on-pulse signal when a voltage of a second node coupled directly to a second end of the second inductor and coupled directly to the output diode becomes a zero voltage; and

an SR flip-flop configured to turn on the power switch based on the on-pulse signal.

12. The switch control circuit of claim 11 , wherein the switch control circuit is configured to turn off the power switch based on a result of a comparison between an error voltage a sense voltage corresponding to a current flowing through the power switch.

13. The switch control circuit of claim 12 , further comprising:

an error amplifier configured to generate the error voltage by amplifying a difference between the output voltage and a predetermined reference voltage; and

a PWM controller configured to compare the error voltage with the sense voltage based on the current flowing through the power switch and generate an off signal to turn off the power switch based on the comparison result.

14. The switch control circuit of claim 13 , wherein the SR flip-flop comprises a set end configured to receive the on-pulse signal and a reset end R configured to receive the off signal, the SR flip-flop being configured to generate a gate voltage to turn on the power switch based on the on-pulse signal and a gate voltage to turn off the power switch according to the off-pulse signal.

15. The switch control circuit of claim 11 , further comprising a clamp configured to receive and clamp a voltage of the node coupled to the second inductor to a first clamping voltage when the voltage of the node is higher than a first clamping reference voltage, the clamp being further configured to clamp the voltage of the node to a second clamping voltage when the voltage of the node is lower than a second clamping reference voltage.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044361/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2013
From: LEE, JAE-YONG; LEE, YOUNG SIK; PARK, YOUNG-BAE; LEE, YOUNG-JE; JANG, EUNSUNG
To: FAIRCHILD KOREA SEMICONDUCTOR LTD
Reel/Frame 030375/0224 →