IP Library Patent Application 13892171
Patent Application
App. No. 13/892,171

CASCADE LED DRIVER AND CONTROL METHODS

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Patent No.
US None
App. No.
13/892,171
Abstract

An electrical circuit is disclosed and methods for controlling the same. The electrical circuit may comprise a plurality of color strings coupled in series, where each color string has at least one lamp, preferably a light emitting diode. Improved efficiency may be accomplished in some embodiments using certain of the disclosed systems and methods.

Claims (48)

1 . A circuit for controlling a plurality of output diodes, the circuit comprising:

a first diode comprising a cathode terminal and an anode terminal;

a second diode comprising a cathode terminal and an anode terminal;

a first switch comprising a first terminal and a second terminal;

a second switch comprising a first terminal and a second terminal;

a capacitor comprising a first terminal and a second terminal;

a first output terminal; and

a second output terminal, wherein

the cathode terminal of the first diode is in electrical communication with the first output terminal,

the cathode terminal of the second diode is in electrical communication with the anode terminal of the first diode, and

the first terminal of the capacitor is in electrical communication with the cathode terminal of the first diode and the second terminal of the capacitor is in electrical communication with the anode terminal of the second diode.

2 . The circuit of claim 1 , wherein the plurality of output diodes comprise a first input terminal and a second input terminal, wherein the first input terminal is in electrical communication with the first output terminal and the second input terminal is in electrical communication with the second output terminal.

3 . The circuit of claim 2 , wherein the first terminal of the capacitor is in electrical communication with the first output terminal and the second terminal of the capacitor is in electrical communication with the second output terminal.

4 . The circuit of claim 1 , wherein the first switch further comprises an input terminal and the second switch comprises an input terminal.

5 . The circuit of claim 4 , wherein the input terminal of the first switch is configured to receive a signal and the input terminal of the second switch is configured to receive a complement of the signal.

6 . The circuit of claim 5 , wherein the complement of the signal comprises a “not” gate.

7 . The circuit of claim 1 , wherein the output diodes are LEDs.

8 . The circuit of claim 1 , wherein,

the first terminal of the first switch is in electrical communication with the cathode terminal of the first diode,

the second terminal of the first switch is in electrical communication with the anode terminal of the first diode,

the first terminal of the second switch is in electrical communication with the cathode terminal of the second diode, and

the second terminal of the second switch is in electrical communication with the anode terminal of the second diode.

9 . The circuit of claim 8 , where the circuit is configured to increase the voltage between the first output terminal and the second output terminal when the first switch is closed and the second switch is open.

10 . The circuit of claim 1 , wherein the capacitor is configured to deliver current to the plurality of diodes.

11 . A method for controlling a circuit in communication with a plurality of diodes, the method comprising:

performing a plurality of iterations;

for at least one of the plurality of iterations:

activating a signal line if a digit in a binary string is one.

12 . The method of claim 11 , wherein the circuit is the circuit of claim 1 .

13 . The method of claim 11 , wherein,

the circuit is the circuit of claim 5 , and wherein,

the signal line is in electrical communication with the input terminal of the first switch and the input terminal of the second switch.

14 . The method of claim 11 , the method further comprising, for the at least one of the plurality of iterations:

setting the digit in the binary string to one to achieve a resulting binary string number; and

adding the resulting binary string number to a fixed value.

15 . The method of claim 14 , wherein the fixed value is associated with a percentage of a period of time that a current flows through a portion of the circuit.

16 . A non-transitory, computer-readable medium comprising instructions configured to cause one or more processors to perform a method comprising the steps:

performing a plurality of iterations;

for at least one of the plurality of iterations:

activating a signal line if a digit in a binary string is one.

17 . The non-transitory, computer-readable medium of claim 16 , wherein the circuit is the circuit of claim 1 .

18 . The non-transitory, computer-readable medium of claim 16 , wherein,

the circuit is the circuit of claim 5 , and wherein,

the signal line is in electrical communication with the input terminal of the first switch and the input terminal of the second switch.

19 . The non-transitory, computer-readable medium of claim 16 , wherein the method further comprises, for the at least one of the plurality of iterations:

setting the digit in the binary string to one to achieve a resulting binary string number; and

adding the resulting binary string number to a fixed value.

20 . The non-transitory, computer-readable medium of claim 19 , wherein the fixed value is associated with a percentage of a period of time that a current flows through a portion of the circuit.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Dec 23, 2019
From: PIVOTAL CAPITAL FUND, LP
To: LUMENETIX, INC.
Reel/Frame 051357/0741 →
SECURITY INTEREST Recorded Aug 31, 2017
From: LUMENETIX, INC.
To: WESTERN ALLIANCE BANK
Reel/Frame 043467/0273 →
SECURITY INTEREST Recorded Sep 16, 2015
From: LUMENETIX, INC.
To: PRIVOTAL CAPITAL FUND, LP
Reel/Frame 036584/0113 →