IP Library Granted Patent US 9,021,331
Granted Patent B2
US 9,021,331 · App. 13/893,832 · Granted Apr 28, 2015

Method and apparatus for generation of soft decision error correction code information

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Quick Facts
Patent No.
US 9,021,331
App. No.
13/893,832
Granted
Apr 28, 2015
Kind
B2
Abstract

A method and apparatus for generating soft decision error correction code information. The method includes generating or creating a lookup table (LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the data in a flash memory device using the soft decision information provided by the lookup table and assigned to the appropriate cells of the flash memory device.

Claims (28)

1. A method for providing soft decision information for error correction codes for a flash memory device, comprising:

generating an offline lookup table of characteristic values of the flash memory device;

loading the lookup table into a solid state device (SSD) controller to which the flash memory device is coupled;

accessing the lookup table to assign characteristic values to one or more cells of the flash memory device; and

decoding data in the flash memory device using the characteristic values provided by the lookup table and assigned to the one or more cells of the flash memory device to provide soft decision information for error correction codes.

2. The method as recited in claim 1 , wherein the lookup table is a log likelihood ratio (LLR) lookup table.

3. The method as recited in claim 1 , wherein the lookup table is a log likelihood ratio (LLR) lookup table based on a plurality of program-erase cycles (PEC) and retention times for the flash memory device.

4. The method as recited in claim 1 , wherein the lookup table is loaded into the solid state device controller during the manufacture of the solid state device controller.

5. The method as recited in claim 1 , wherein the lookup table is loaded into the solid state device controller after the solid state device controller has been manufactured.

6. A solid state device (SSD) controller, comprising:

a processor;

a processor memory device coupled to the processor;

a lookup table loaded into the memory device of characteristic values of a flash memory device coupled to the solid state device controller,

wherein the processor is configured to access the lookup table to assign characteristic values to one or more cells of the flash memory device, and

wherein the processor is configured to decode data in the flash memory device using the characteristic values provided by the lookup table and assigned to the one or more cells of the flash memory device to provide soft decision information for error correction codes.

7. The solid state device controller as recited in claim 6 , wherein the lookup table is a log likelihood ratio (LLR) lookup table.

8. The solid state device controller as recited in claim 6 , wherein the lookup table is a log likelihood ratio (LLR) lookup table based on a plurality of program-erase cycles (PEC) and retention times for the flash memory device.

9. The solid state device controller as recited in claim 6 , wherein the lookup table is loaded into the solid state device controller during the manufacture of the solid state device controller.

10. The solid state device controller as recited in claim 6 , wherein the lookup table is loaded into the solid state device controller after the solid state device controller has been manufactured.

11. A non-transitory computer readable medium storing instructions that carry out a method for providing soft decision information for error correction codes for a flash memory device, the method comprising:

instructions for generating an offline lookup table of characteristic values of the flash memory device;

instructions for loading the lookup table into a solid state device (SSD) controller to which the flash memory device is coupled;

instructions for accessing the lookup table to assign characteristic values to one or more cells of the flash memory device; and

instructions for decoding data in the flash memory device using the characteristic values provided by the lookup table and assigned to the one or more cells of the flash memory device to provide soft decision information for error correction codes.

12. The non-transitory computer readable medium as recited in claim 11 , wherein the lookup table is a log likelihood ratio (LLR) lookup table.

13. The non-transitory computer readable medium as recited in claim 11 , wherein the lookup table is a log likelihood ratio (LLR) lookup table based on a plurality of program-erase cycles (PEC) and retention times for the flash memory device.

14. The non-transitory computer readable medium as recited in claim 11 , wherein the lookup table is loaded into the solid state device controller during the manufacture of the solid state device controller.

15. The non-transitory computer readable medium as recited in claim 11 , wherein the lookup table is loaded into the solid state device controller after the solid state device controller has been manufactured.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034771/0272 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2013
From: WU, YUNXIANG; CHEN, ZHENGANG; HARATSCH, ERICH F.
To: LSI CORPORATION
Reel/Frame 030442/0711 →