Granted Patent B2

US 9,659,061 · App. 13/894,353 · Granted May 23, 2017

Abstract

Claims (57)

1. A method of performing space-efficient data query operations, comprising:

interning fields of a plurality of multi-field records to produce interned records representing the multi-field records;

receiving a query to compute a result over the plurality of multi-field records;

initializing a sparse bit set, said sparse bit set sized to accommodate a number of distinct values present in one of the fields of the plurality of multi-field records;

dividing the interned records into two classes according to the query; and

setting a bit in the sparse bit set for each interned record of one of the two classes, wherein

an in-memory representation of the sparse bit set, exclusive of overhead, occupies fewer bits than the number of distinct values present in the one of the fields of the plurality of multi-field records.

2. The method of claim 1 wherein the in-memory representation of the sparse bit set comprises a plurality of blocks, all but one of which represent a number of bits that is a power-of-two multiple of a natural word size, and each such block containing exactly one of:

all clear bits; or

all set bits; or

a subordinate plurality of blocks of recursive structure, all of such blocks having a power-of-two size; or

the power-of-two multiple number of bits, each bit thereof in either a clear state or a set state.

3. The method of claim 1 wherein the sparse bit set is a first sparse bit set, the method further comprising:

repeating the receiving, initializing, dividing and setting operations to produce a second sparse bit set; and

creating a third sparse bit set as a two-operand function of the first sparse bit set and the second sparse bit set.

4. The method of claim 3 wherein the two-operand function is one of a union, an intersection, or an exclusive or of the first sparse bit set and the second sparse bit set.

5. The method of claim 1 , further comprising:

determining a number of clear bits in the sparse bit set.

6. The method of claim 1 , further comprising:

determining a number of set bits in the sparse bit set.

7. A method for improving access speed for a key-value dictionary, comprising:

initializing a sparse bit set and a key-value dictionary;

receiving an integer-valued key and a corresponding value;

setting a bit in the sparse bit set corresponding to the integer-valued key;

inserting a key-value binding into the key-value dictionary, a key of said key-value binding equal to the integer-valued key, and a value of the key-value binding equal to the corresponding value;

repeating the receiving, setting and inserting operations;

receiving an integer-valued search key;

examining a bit in the sparse bit set corresponding to the integer-valued search key;

if the bit in the sparse bit set corresponding to the integer-valued search key is clear, returning a default value; and

if the bit in the sparse bit set corresponding to the integer-valued search key is set, searching the key-value dictionary for the integer-valued search key and returning a value from a key-value binding corresponding to the integer-valued search key.

8. The method of claim 7 wherein the default value indicates that the key-value dictionary does not contain a value corresponding to the integer-valued search key.

9. The method of claim 7 wherein the integer-valued key is an integer from a densely-utilized range of integers.

10. The method of claim 9 , further comprising:

receiving a non-integer-valued key;

converting the non-integer-valued key to a corresponding integer drawn from a densely-utilized range of integers; and

using the corresponding integer as the integer-valued key.

11. A non-transitory computer-readable medium containing instructions and data to cause a programmable processor to perform operations comprising:

initializing a sparse bit set structure to accommodate a predetermined number of bits with a predetermined initial value, said sparse bit set structure occupying fewer bits in a memory of the programmable processor than the predetermined number of bits;

modifying the sparse bit set structure to represent one bit with a complement of the predetermined initial value, a remainder of said predetermined number of bits retaining their previous values, said modification yielding a modified sparse bit set structure that occupies fewer bits in the memory of the programmable processor than the predetermined number of bits;

accessing the modified sparse bit structure to retrieve a current value of an identified one of the predetermined number of bits; and

returning the current value of the identified one of the predetermined number of bits.

12. The non-transitory computer-readable medium of claim 11 , containing additional data and instructions to cause the programmable processor to perform operations comprising:

concatenating the sparse bit set structure with a second sparse bit set structure to produce a third sparse bit set structure representing a number of bits no smaller than a sum of the predetermined number of bits and a second predetermined number of bits represented by the second sparse bit set structure, said third sparse bit set structure occupying fewer bits in the memory of the programmable processor than the sum of the predetermined number of bits and the second predetermined number of bits.

13. The non-transitory computer-readable medium of claim 11 , containing additional data and instructions to cause the programmable processor to perform operations comprising:

computing a Boolean operation between the sparse bit set structure and a second sparse bit set structure to produce a third sparse bit set structure representing a number of bits no smaller than a greater of the predetermined number of bits and a second predetermined number of bits represented by the second sparse bit set structure, said third sparse bit set structure occupying fewer bits in the memory of the programmable processor than the sum of the predetermined number of bits and the second predetermined number of bits.

14. The non-transitory computer-readable medium of claim 13 wherein the Boolean operation is one of AND, NAND, OR, NOR, XOR or XNOR.

15. The non-transitory computer-readable medium of claim 11 , containing additional data and instructions to cause the programmable processor to perform operations comprising:

computing a unary operation on the sparse bit set structure to produce a second sparse bit set structure representing at least the predetermined number of bits, said second sparse bit set structure occupying fewer bits in the memory of the programmable processor than the predetermined number of bits.

16. The non-transitory computer-readable medium of claim 11 wherein the sparse bit set structure comprises at least one leaf node, and wherein each of the at least one leaf node represents one of:

a plurality of clear (“ZERO”) bits;

a plurality of set (“ONE”) bits; or

a plurality of literal bits.

17. The non-transitory computer-readable medium of claim 16 wherein modifying the sparse bit set structure comprises:

splitting the at least one node into a plurality of child nodes, said plurality of child nodes representing a number of bits equal to a number of bits represented by the at least one node; and wherein

the plurality of child nodes represent a substantially identical plurality of bits as the at least one node, except that the plurality of child nodes represent a single changed bit value from the plurality of bits of the at least one node.

18. The non-transitory computer-readable medium of claim 11 , containing additional data and instructions to cause the programmable processor to perform operations comprising:

optimizing the sparse bit structure to represent an identical predetermined number of bit values while occupying fewer bits in the memory than the lesser of the predetermined number of bits and a number of bits in the memory occupied by the sparse bit structure prior to the optimizing operation.

Assignments (10)