IP Library Granted Patent US 9,218,737
Granted Patent B2
US 9,218,737 · App. 13/894,444 · Granted Dec 22, 2015

Receiving control circuit for a wall control interface with phase modulation and detection for power management

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Quick Facts
Patent No.
US 9,218,737
App. No.
13/894,444
Granted
Dec 22, 2015
Kind
B2
Abstract

A wall control interface for power management includes a transmitting circuit that generates a switching signal to control a switch and achieve a phase modulation to a power line signal in response to a transmitting-data. A receiving circuit is coupled to detect the phase of the power line signal for generating a data signal and a receiving-data in response to the phase of the power line signal. The receiving circuit further generates a control signal to control power of a load in accordance with the data signal or the receiving-data. The phase modulation is achieved by controlling a turn-on angle of the power line signal. The switch remains in a turn-on state during the normal condition, which achieves good power and low current harmonic. The phase modulation is only performed during the communication of the power management.

Claims (16)

1. A receiving control circuit for a wall control interface, comprising:

a phase-detection circuit, coupled to receive a power line signal for generating a data signal in accordance with the phase of the power line signal; and

a control circuit, receiving the data signal for generating a control signal coupled to control power of a load,

wherein the data signal is correlated to a duty cycle of the power line signal, and the data signal is generated in response to a turn-on angle of the power line signal and a pulse signal.

2. The receiving control circuit as claimed in claim 1 , the phase detection circuit comprising:

a rectifier and an attenuator, coupled to receive the power line signal for generating an attenuated signal; and

a comparator, coupled to receive the attenuated signal for generating the data signal,

wherein the data signal is generated by comparing the attenuated signal with a threshold.

3. The receiving control circuit as claimed in claim 1 , wherein the control circuit comprises a low-pass filter for generating a second control signal in accordance with the pulse width of the data signal.

4. The receiving control circuit as claimed in claim 1 , wherein the control circuit further comprises a normalization circuit for generating a normalized signal in response to the data signal, the normalized signal is a digital signal, and a value of a high-state of the normalized signal is a constant.

5. The receiving control circuit as claimed in claim 1 , wherein the control circuit comprising:

a digital-to-analog converter, generating a first control signal in accordance with the receiving-data;

a normalization circuit and a low-pass filter, generating a second control signal in accordance with the data signal;

a comparator, generating a channel-control signal in accordance with the receiving-data; and

output switches, coupled to the first control signal and the second control signal to generate the control signal in accordance with the first control signal or the second control signal,

wherein the output switches are controlled by the channel-control signal.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046410/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042328/0318 →
CHANGE OF NAME Recorded Mar 22, 2017
From: SYSTEM GENERAL CORPORATION
To: FAIRCHILD (TAIWAN) CORPORATION
Reel/Frame 042068/0929 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2017
From: YANG, TA-YUNG; LIN, JENN-YU G.; LIN, YI-CHI; HSUEH, CHENG-CHI
To: SYSTEM GENERAL CORP.
Reel/Frame 041287/0962 →