All digital burst-mode clock and data recovery (CDR)
View Patent ↗The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.
1. A clock and data recovery (CDR) unit comprising:
a bang-bang phase detector configured to receive data and to receive a recovered clock from a phase selector multiplexer and to produce a phase comparison output, the phase comparison output indicating that the recovered clock is early or late, as compared with the received data;
a block to receive the phase comparison output, and to produce a Grey code output, wherein when the block implements a fixed phase recovery operation in response to the phase comparison output indicating that the recovered clock is both early and late, and wherein the fixed phase recovery operation includes advancing the Grey code output for a fixed number of periods greater than one, then returning to normal operation;
the phase selector multiplexer to select a clock phase as the recovered clock signal using the Grey code output.
2. The clock and data recovery unit of claim 1 , wherein the block increments the Grey code output when the early output is high and the late output is low.
3. The clock and data recovery unit of claim 2 , wherein the block decrements the Grey code output when the early output is low and the late output is high.
4. The clock and data recovery data unit of claim 1 , wherein the fixed number of periods is four or more.
5. The clock and data recovery unit of claim 1 , wherein the unit does not use a voltage controlled oscillator (VCO).
6. The clock and data recovery unit of claim 1 , wherein the CDR unit locks the recovered clock to the data within 3 clock cycles.
7. The clock and data recovery unit of claim 1 , wherein the signals through the clock and data recovery unit are such that the switching of the multiplexer does not produce glitches.
8. The clock and data recovery unit of claim 1 , wherein the data is USB input data.
9. A clock and data recovery (CDR) unit comprising:
a phase detector configured to receive data and to receive a recovered clock from a phase selector and to produce a phase comparison output, the phase comparison output indicating that the recovered clock is early or late, as compared with the received data;
a block configured to receive the phase comparison output, and to produce a multiplexer selector control signal, the multiplexer selector control signal being incremented in response to the comparison output indicating that the recovered clock is early, the multiplexer selector control signal being decremented in response to the comparison output indicating that the recovered clock is late, and the block implementing a fixed phase recovery operation in response to the comparison output indicating that the recovered clock is both early and late, wherein the fixed phase recovery operation includes incrementing the multiplexer selector control signal for a fixed number of periods greater than one, then returning to normal operation; and
the phase selector multiplexer to use the multiplexer selector control signal to select a clock phase as the recovered clock signal.
10. The clock and data recovery data unit of claim 9 , wherein the fixed number periods is four or more.
11. The clock and data recovery unit of claim 9 , wherein the unit does not use a voltage controlled oscillator (VCO).
12. The clock and data recovery unit of claim 9 , wherein the CDR unit locks the recovered clock to the data within 3 clock cycles.
13. The clock and data recovery unit of claim 9 , wherein the signals through the clock and data recovery unit are such that the switching of the multiplexer does not produce glitches.
14. The clock and data recovery unit of claim 9 , wherein the data is USB input data.
15. The clock and data recovery unit of claim 9 , wherein the multiplexer selector control signal is a Grey code.
16. The clock and data recovery unit of claim 9 , wherein the phase detector is a bang-bang phase detector.
17. The clock and data recovery unit of claim 9 , further comprising a very early and a very late comparison output of the phase detector; the block further implementing a fixed multi-period operation when the very early or the very late output is high.
18. The clock and data recovery unit of claim 9 , wherein the number of selectable phases is four or more.
19. The clock and data recovery unit of claim 18 , wherein the number of selectable phases is ten.