Crest factor reduction for brand-limited multi-carrier signals
View Patent ↗A crest factor reduction (CFR) circuit reduces the peak-to-average (PAR) power of a digitally modulated signal in a complex baseband is achieved by post-processing the input signal, with negligible increase in out-of-band emissions. The CFR circuit takes advantage of a procedure that solves for an optimum CFR using a constraint-optimization approach. In one embodiment, the CFR circuit, which receives an input signal and provides an output signal, includes: (a) an error generation circuit that receives the input signal and provides an error signal representative of a measure of circuit-induced distortion and a delayed input signal, the delayed input signal being the input signal delayed by a predetermined value; (b) a linear-phase filter receiving the error signal to provide a correction signal; and (c) a summer that subtracts the correction from the delayed input signal to provide the output signal. This circuit can achieve near optimal CFR for arbitrary multi-carrier signals without incurring high computational complexity.
1. A crest factor reduction circuit receiving an input signal and providing an output signal, comprising:
an error generation circuit that receives the input signal and provides an error signal representative of a measure of a circuit-induced distortion, and a delayed input signal, the delayed input signal being the input signal delayed by a predetermined value;
a linear-phase filter receiving the error signal to provide a correction signal; and
a summer that subtracts the correction from the delayed input signal to provide the output signal; and
wherein the error generation circuit includes a quantized sparse error (QSE) block including a comparator to generate a sparse, quantized output signal which forms the error signal, and which is applied to the linear-phase filter, the comparator determining whether or not each sample in the input signal applied to the QSE block satisfies a predetermined condition, and when the predetermined condition is satisfied provides non-zero samples in the sparse, quantized output signal.
2. The crest factor reduction circuit of claim 1 , wherein the linear phase filter has a frequency response that is expressed as A(ω)e −jωD , where D is a delay of the linear phase filter, A(ω) is a non-negative real-value frequency response, and ω is the frequency variable.
3. The crest factor reduction circuit of claim 1 , wherein the error generation circuit comprises one or more error generation stages.
4. The crest factor reduction circuit of claim 3 , wherein the input signal includes multiple carrier signals.
5. The crest factor reduction circuit of claim 3 , wherein each said error generation stage comprises a high-pass filter, a polar-clipping-error block and a delay circuit matching the delayed input signal to a delay of the polar-clipping-error block.
6. The crest factor reduction circuit of claim 5 , wherein the high pass filter has a frequency response that is expressed as [1−A(ω)]e −jωD , where D is a delay of the linear phase filter, A(ω) is a non-negative real-value frequency response, and ω is the frequency variable.
7. The crest factor reduction circuit of claim 5 , wherein the polar-clipping error block implements a non-zero, non-linear function for an input complex sample having a magnitude greater than a predetermined value.
8. The crest factor reduction circuit of claim 3 , wherein each said error generation stage comprises:
a quantized sparse error (QSE) block that receives as an input a block input signal from a previous one of said one or more error generation stages, and provides a sparse quantized output signal;
an error filter that provides a filtered quantized output signal from the sparse quantized output signal;
a delay element that delays the block input signal by a time period matching a delay of the error filter; and
a summer that subtracts the filtered quantized output signal from the delayed block input signal to provide a block output signal. new
9. The crest factor reduction circuit of claim 8 , wherein the error filter comprises:
a tapped delay line that receives a number of complex samples from the sparse quantized output signal over a plurality of periods of an input clock;
a plurality of summers that combine the complex samples received over the clock periods to provide a plurality of complex sums;
a plurality of multipliers for multiplying the complex sums with a plurality of filter coefficients to provide a plurality of complex products; and
an output summer for summing the complex products.
10. The crest factor reduction circuit of claim 9 , wherein the summers and the multipliers operate at a higher clock rate than the input sampling rate, such that multiple summing and multiplication operations are performed within each input sampling period.
11. The crest factor reduction circuit of claim 8 , wherein the error filter comprises:
a plurality of registers each provided to store a non-zero complex sample from the sparse quantized output signal and a corresponding life time index representing a number of clock periods of the sparse quantized output signal since the non-zero complex sample is stored into the register;
a plurality of processing circuits that receives the non-zero complex samples and their corresponding life time indices stored in the registers, each processing circuit comprising:
a random access memory circuit that receive one or more of the life time indices as addresses to provide corresponding filter coefficients stored in the random access memory circuit;
a multiplier that receives in a predetermined order one or more of the non-zero complex samples and the corresponding filter coefficients to provide corresponding products; and
an accumulator for summing the corresponding products to provide an accumulated sum; and
a summer for summing the accumulated sums of the processing circuits to provide samples in the filtered quantized output signal.
12. The crest factor reduction circuit of claim 11 , wherein each said processing circuit is configured to provide a plurality of non-zero complex samples over each clock period of the sparse quantized output signal.
13. The crest factor reduction circuit of claim 8 , wherein the sparse quantized output signals of the error generation stages are delayed and summed to provide the error signal.
14. The crest factor reduction circuit of claim 8 , wherein the error signal is provided for error vector magnitude monitoring.
15. The crest factor reduction circuit of claim 8 , wherein the error filter comprises a linear phase finite impulse response filter.
16. The crest factor reduction circuit of claim 1 , wherein the predetermined condition is satisfied when the instantaneous power is higher than a threshold and not lower than the adjacent sample powers.
17. The crest factor reduction circuit of claim 1 , wherein the comparator generates a binary output as a function of multiple consecutive samples in the block input signal.
18. The crest factor reduction circuit of claim 1 , further comprising a non-linear gain circuit that provides a non-linear gain to the block output signal.
19. The crest factor reduction circuit of claim 1 , wherein the quantized sparse error (QSE) block has a resolution that is a multiple of the least significant bit of a sample in the block input signal.
20. The crest factor reduction circuit of claim 1 , wherein the block output signal has a substantially white power spectrum.
21. The crest factor reduction circuit of claim 1 , further comprising:
a spectrum analysis circuit for determining power spectra of the input signal; and
a crest factor reduction controller that receives the power spectra to provide a set of filter coefficients for the error filter.
22. The crest factor reduction circuit of claim 21 , wherein the spectrum analysis circuit computes fast fourier transforms.
23. The crest factor reduction circuit of claim 21 , wherein the crest factor reduction controller varies the set of filter coefficients adaptively based on the power spectra received.
24. The crest factor reduction circuit of claim 21 , wherein the crest factor reduction controller extracts carrier-power distributions from the power spectra.
25. An error generation stage, which comprises:
a quantized error block that receives a block input signal and provides a quantized output signal;
an error filter that provides a filtered quantized output signal from the quantized output signal;
a delay element that delays the block input signal by a time period matching a delay of the error filter; and
a summer that subtracts the filtered quantized output signal from the delayed block input signal to provide a block output signal; and
a comparator configured in the quantized error block that determines when each sample in the block input signal satisfies a predetermined condition, and provides non-zero samples in the quantized output signal whenever said predetermined condition is satisfied.
26. The error generation stage of claim 25 , wherein the predetermined condition is satisfied when the instantaneous power is higher than a threshold and not lower than the adjacent sample powers.
27. The error generation stage of claim 25 , wherein the comparator logs generates a binary output as a function of multiple consecutive samples in the block input signal.
28. The error generation stage of claim 25 , further comprising a non-linear gain circuit that provides a non-linear gain to the block output signal.
29. The error generation stage of claim 25 , wherein the quantizer has a resolution that is a multiple of the least significant bit of a sample in the block input signal.
30. The error generation stage of claim 25 , wherein the block output signal has a white power spectrum.
31. The error generation stage of claim 25 , wherein the error generation stage is one of a plurality of error generation stages cascaded in a predetermined manner to process an input signal that is modulated by multiple carriers.
32. An error filter, which comprises:
a tapped delay line that receives a number of complex samples from a quantized output signal over a plurality of periods of an input clock;
a plurality of summers that combines the complex samples received over the clock periods to provide a plurality of complex sums;
a plurality of multipliers for multiplying the complex sums with a plurality of filter coefficients to provide a plurality of complex products, wherein each one of the plurality of multipliers is configured to consume no power whenever a received one of the complex sums is zero; and
an output summer for summing the complex products.
33. The error filter of claim 32 , wherein the summers and the multipliers operate at a higher clock rate than the input sampling rate, such that multiple summing and multiplication operations are performed within each input sampling period.
34. An error filter, which comprises:
a plurality of registers each provided to store a non-zero complex sample from the quantized output signal and a corresponding life time index representing a number of clock periods of the quantized output signal since the non-zero complex sample is stored into the register;
a plurality of processing circuits that receive the non-zero complex samples and their corresponding life time indices stored in the registers, each processing circuit comprising:
a random access memory circuit that receives one or more of the life time indices as addresses to provide corresponding filter coefficients stored in the random access memory circuit;
a multiplier that receives in a predetermined order one or more of the non-zero complex samples and the corresponding filter coefficients to provide corresponding products; and
an accumulator for summing the corresponding products to provide an accumulated sum; and
a summer for summing the accumulated sums of the processing circuits to provide samples in the filtered quantized output signal.
35. The error filter of claim 34 , wherein each said processing circuit is configured to provide a plurality of non-zero complex samples over each said clock period of the quantized output signal.