Nonvolatile semiconductor memory
View Patent ↗A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.
1. A nonvolatile semiconductor memory comprising:
a first transistor;
a second transistor;
memory cell unit including memory cells electrically connected in series between the first transistor and the second transistor;
a source line electrically connected to the first transistor;
a bit line electrically connected to the second transistor;
word lines electrically connected to gates of the memory cells;
a sense amplifier including a first node, a third transistor, a fourth transistor and a first capacitor, one end of the third transistor being electrically connected to the bit line, the other end of the third transistor being electrically connected to the first node, one end of the fourth transistor being electrically connected to both the first node and the other end of the third transistor, and one end of the first capacitor being electrically connected to the first node; and
a controller configured to perform a verify operation on a condition that a verify voltage is applied to a first word line selected from the word lines and a first voltage is applied to a gate of the fourth transistor, and a second voltage is applied to a gate of the third transistor twice during applying the first voltage to the gate of the fourth transistor, the second voltage being higher than the first voltage.
2. The memory of claim 1 , wherein a third voltage is applied to the other end of the first capacitor, the third voltage being higher than zero voltage.
3. The memory of claim 2 , further comprising:
a word line driver disposed adjacent to a memory cell array in a first direction, the memory cell array including the first transistor, the second transistor, the memory cell unit, the source line, the bit line and the word lines; and
wherein the sense amplifier is disposed adjacent to a memory cell array in a second direction, the second direction being orthogonal to the first direction.
4. The memory of claim 3 , wherein the sense amplifier includes a first latch circuit and a second latch circuit, and each of the memory cells is capable of holding three or more level data.
5. The memory of claim 4 , wherein the first voltage is substantially zero voltage.
6. The memory of claim 4 , wherein the first voltage is a voltage for turning off the fourth transistor.
7. The memory of claim 3 , wherein the first voltage is substantially zero voltage.
8. The memory of claim 3 , wherein the first voltage is a voltage for turning off the fourth transistor.
9. The memory of claim 1 , further comprising:
a word line driver disposed adjacent to a memory cell array in a first direction, the memory cell array including the first transistor, the second transistor, the memory cell unit, the source line, the bit line and the word lines; and
wherein the sense amplifier is disposed adjacent to a memory cell array in a second direction, the second direction being orthogonal to the first direction.
10. The memory of claim 9 , wherein the sense amplifier includes a first latch circuit and a second latch circuit, and each of the memory cells is capable of holding three or more level data.
11. The memory of claim 1 , wherein the sense amplifier includes a first latch circuit and a second latch circuit, and each of the memory cells is capable of holding three or more level data.
12. The memory of claim 11 , wherein the first voltage is substantially zero voltage.
13. The memory of claim 11 , wherein the first voltage is a voltage for turning off the fourth transistor.
14. The memory of claim 1 , wherein the first voltage is substantially zero voltage.
15. The memory of claim 1 , wherein the first voltage is a voltage for turning off the fourth transistor.