Efficient storage of error correction information in DRAM

1. A non-transitory computer accessible storage medium having program instructions stored therein that, in response to execution by a computer system, causes the computer system to perform operations including:

encoding input data with an Error Correction Code (ECC), to produce encoded data;

formatting the encoded data in a super-frame including a given number of burst sequences arranged in parallel, each burst sequence including of one or more bursts of multiple bytes of the encoded data; and

storing, in parallel, the burst sequences of the super-frame in respective memories devices over a single data bus having a bus width, in bytes, that is equal to the given number.

2. The non-transitory computer accessible storage medium of claim 1 , wherein the given number is not an integer power of two.

3. The non-transitory computer accessible storage medium of claim 1 , wherein the give number is three, and the bus width is three bytes.

4. The non-transitory computer accessible storage medium of claim 1 , wherein the encoded data comprises data bits and redundancy bits, and wherein formatting the encoded data comprises interleaving the data bits and the redundancy bits in the super-frame.

5. The non-transitory computer accessible storage medium of claim 1 , wherein formatting the encoded data comprises filling all the bytes in the super-frame with the encoded data.

6. The non-transitory computer accessible storage medium of claim 1 , wherein the memory devices comprise Dynamic Random Access Memory (DRAM) devices.

7. The non-transitory computer accessible storage medium of claim 1 , further comprising receiving the input data in blocks.

8. A memory controller, comprising:

an error correction unit configured to:

receive input data; and

encode the received input data with an Error Correction Code (ECC); and

a storage unit configured to:

format the encoded data in a super-frame, wherein the super-frame includes a given number of burst sequences arranged in parallel, each bust sequence include one or more bursts of multiple bytes of encoded data; and

store, in parallel, the burst sequences in respective memory devices over a single data bus, wherein the single data bus has a bus width, in bytes, equal to the give number.

9. The memory controller of claim 8 , wherein the given number is not an integer power of two.

10. The memory controller of claim 8 , wherein the storage unit is further configured to store the burst sequences in the respective memory devices over respective portions of the bus width.

11. The memory controller of claim 8 , wherein the storage unit is further configured to read the super-frame from the memory devices after storing the burst sequences.

12. The memory controller of claim 11 , wherein the error correction unit is further configured to decode the ECC of the read super-frame.

13. The memory controller of claim 8 , wherein the encoded data includes data bits and redundancy bits.

14. The memory controller of claim 13 , wherein to format the encoded data, the storage unit is further configured to interleave the data bits and the redundancy bits in the super-frame.

15. A memory system, comprising:

a given number of memory devices;

a data bus coupled to the given number of memory devices

a memory controller configured to:

receive input data;

encode the input data with an Error Correction Code (ECC);

format the encoded data in a super-frame, wherein the super-frame includes the given number of burst sequences arranged in parallel, wherein each burst sequence includes one or more bursts of multiple bytes;

store, in parallel, the burst sequences in the respective memory devices over the data bus.

16. The memory system of claim 15 , wherein the given number is not an integer power of two.

17. The memory system of claim 15 , wherein the give number is three, and the bus width is three bytes.

18. The memory system of claim 15 , wherein the encoded data comprises data bits and redundancy bits.

19. The memory system of claim 18 , wherein to format the encoded data, the memory controller is further configured to interleave the data bits and the redundancy bits into the super-frame.

20. The memory system of claim 15 , wherein to format the encoded data the memory controller is further configured to fill all the bytes in the super-frame with the encoded data.