IP Library Granted Patent US 8,607,131
Granted Patent B2
US 8,607,131 · App. 13/900,264 · Granted Dec 10, 2013

Decoder, receiving apparatus, decoding method, and receiving method

Inventors: Yutaka Murakami (Osaka, JP); Shutai Okamura (Osaka, JP)
Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 8,607,131
App. No.
13/900,264
Granted
Dec 10, 2013
Kind
B2
Abstract

Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

Claims (338)

1. A decoder comprising:

a log likelihood ratio calculation section that calculates first log likelihood ratio sequence using second coded sequence formed by removing bits in first coded sequence s,

the first coded sequence s satisfying equation 1-1, equation 1-2 and equation 1-3, and being made up of z×n b bits from a first bit to a z×n b -th bit,

the equation 1-1, equation 1-2 and equation 1-3 being generated for first bit information bit sequence u,

the second coded sequence being formed by removing the bits from a z×y+1-th bit to a z×(y+1)-th bit (y is an integer between 0 and (n b −1)) in the first coded sequence s based on a y-th puncturing pattern, and

the y-th puncturing pattern corresponding to the number of columns z ranging from z×y+1 columns to z×(y+1) columns and having a cycle of divisors of the number of columns z;

an insertion section that generates second log likelihood ratio sequence in which a predetermined log likelihood ratio is inserted to the first log likelihood ratio sequence based on the y-th puncturing pattern; and

a BP decoding section that decodes the second log likelihood ratio sequence based on the parity check matrix H and outputs the first information bit sequence u:

GH T =0  (Equation 1-1)

s T =Gu T   (Equation 1-2)

Hs= 0  (Equation 1-3)

where H is a parity check matrix of an low density parity check code of (z×m b ) rows and (z×n b ) columns configured by arranging submatrixes of z rows and z columns in m b rows and n b columns, G is a generator matrix holding a relationship of equation 1-1 with the parity check matrix H of the low density parity check code and the first coded sequence s is a coded sequence made up of z×n b bits.

2. The decoder according to claim 1 , wherein the parity check matrix H of the low density parity check code is defined by equation 2:

H

=

[

P

0

,

0

P

0

,

1

P

0

,

2

P

0

,

n

b

-

2

P

0

,

n

b

-

1

P

1

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0

P

1

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1

P

1

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2

P

1

,

n

b

-

2

P

1

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n

b

-

1

P

2

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0

P

2

,

1

P

2

,

2

P

2

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n

b

-

2

P

2

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n

b

-

1

P

m

b

-

1

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0

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m

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-

1

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P

m

b

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1

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2

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m

b

-

1

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n

b

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2

P

m

b

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1

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n

b

-

1

]

(

Equation

2

)

where P i,j is a cyclic permutation matrix of a unit matrix of z rows and z columns or zero matrix of z rows and z columns.

3. The decoder according to claim 2 , wherein the low density parity check code is a quasi cyclic low density parity check block code.

4. The decoder according to claim 2 , wherein the low density parity check code is a quasi cyclic low density parity check code.

5. A receiving apparatus comprising:

a receiving section that receives second coded sequence formed by removing bits in first coded sequence s,

the first coded sequence s satisfying equation 3-1, equation 3-2 and equation 3-3, and being made up of z×n b bits from a first bit to a z×n b -th bit,

the equation 3-1, equation 3-2 and equation 3-3 being generated for first information bit sequence u,

the second coded sequence being formed by removing the bits from a z×y+1-th bit to a z×(y+1)-th bit (y is an integer between 0 and (n b −1)) in the first coded sequence s based on a y-th puncturing pattern, and

the y-th puncturing pattern corresponding to the number of columns z ranging from z×y+1 columns to z×(y+1) columns and having a cycle of divisors of the number of columns z;

a log likelihood ratio calculation section that calculates first log likelihood ratio sequence using the second coded sequence;

an insertion section that generates second log likelihood ratio sequence in which a predetermined log likelihood ratio is inserted to the first log likelihood ratio sequence based on the y-th puncturing pattern; and

a BP decoding section that decodes the second log likelihood ratio sequence based on the parity check matrix H and outputs the first information hit sequence u:

GH T =0  (Equation 3-1)

s T =Gu T   (Equation 3-2)

Hs= 0  (Equation 3-3)

where H is a parity check matrix of an low density parity check code of (z×m b ) rows and (z×n b ) columns configured by arranging submatrixes of z rows and z columns in m b rows and n b columns, G is a generator matrix holding a relationship of equation 3-1 with the parity check matrix H of the low density parity check code and the first coded sequence s is a coded sequence made up of z×n b bits.

6. A decoding method comprising the steps of:

calculating first log likelihood ratio sequence using second coded sequence formed by removing bits in first coded sequence s,

the first coded sequence s satisfying equation 4-1, equation 4-2 and equation 4-3, and being made up of z×n b bits from a first bit to a z×n b -th bit,

the equation 4-1, equation 4-2 and equation 4-3 being generated for first information hit sequence u,

the second coded sequence being formed by removing the bits from a z×y+1-th bit to a z×(y+1)-th bit (y is an integer between 0 and (n b −1)) in the first coded sequence s based on a y-th puncturing pattern, and

the y-th puncturing pattern corresponding to the number of columns z ranging from z×y+1 columns to z×(y+1) columns and having a cycle of divisors of the number of columns z;

generating second log likelihood ratio sequence in which a predetermined log likelihood ratio is inserted to the first log likelihood ratio sequence based on the y-th puncturing pattern;

decoding the second log likelihood ratio sequence based on the parity check matrix H; and

outputting the first information bit sequence u:

GH T =0  (Equation 4-1)

s T =Gu T   (Equation 4-2)

Hs= 0  (Equation 4-3)

where H is a parity check matrix of an low density parity check code of (z×m b ) rows and (z×n b ) columns configured by arranging submatrixes of z rows and z columns in m b rows and n b columns, G is a generator matrix holding a relationship of equation 4-1 with the parity check matrix H of the low density parity check code and the first coded sequence s is a coded sequence made up of z×n b bits.

7. The decoding method according to claim 6 , wherein the parity check matrix H of the low density parity check code is defined by equation 5:

H

=

[

P

0

,

0

P

0

,

1

P

0

,

2

P

0

,

n

b

-

2

P

0

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n

b

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1

P

1

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m

b

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1

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n

b

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2

P

m

b

-

1

,

n

b

-

1

]

(

Equation

5

)

where P i,j is a cyclic permutation matrix of a unit matrix of z rows and z columns or zero matrix of z rows and z columns.

8. The decoding method according to claim 7 , wherein the low density parity check code is a quasi cyclic low density parity check block code.

9. The decoding method according to claim 7 , wherein the low density parity check code is a quasi cyclic low density parity check code.

10. A receiving method comprising the steps of:

receiving second coded sequence formed by removing bits in first coded sequence s,

the first coded sequence s satisfying equation 6-1, equation 6-2 and equation 6-3, and being made up of z×n b bits from a first bit to a z×n b -th bit,

the equation 6-1, equation 6-2 and equation 6-3 being generated for first information bit sequence u,

the second coded sequence being formed by removing the bits from a z×y+1-th bit to a z×(y+1)-th bit (y is an integer between 0 and (n b −1)) in the first coded sequence s based on a y-th puncturing pattern, and

the y-th puncturing pattern corresponding to the number of columns z ranging from z×y+1 columns to z×(y+1) columns and having a cycle of divisors of the number of columns z;

calculating first log likelihood ratio sequence using the second coded sequence;

generating second log likelihood ratio sequence in which a predetermined log likelihood ratio is inserted to the first log likelihood ratio sequence based on the y-th puncturing pattern;

decoding the second log likelihood ratio sequence based on the parity check matrix H; and

outputting the first information bit sequence u:

GH T =0  (Equation 6-1)

s T =Gu T   (Equation 6-2)

Hs= 0  (Equation 6-3)

where H is a parity check matrix of an low density parity check code of (z×m b ) rows and (z×n b ) columns configured by arranging submatrixes of z rows and z columns in m b rows and n b columns, G is a generator matrix holding a relationship of equation 6-1 with the parity check matrix H of the low density parity check code and the first coded sequence s is a coded sequence made up of z×n b bits.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 033033/0163 →
Priority Claims (2)
JP 2008-264382 · Oct 10, 2008 · national
JP 2008-290022 · Nov 12, 2008 · national
Continuity (2)
Continuation 13122942
Related Publication 20130262955A1 · Oct 3, 2013