Semiconductor device
View Patent ↗A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.
1. A device comprising:
first and second bit lines;
an amplifier circuit coupled to the first and second bit lines;
a first transistor coupled to the amplifier circuit and cooperating with the amplifier circuit to serve as a sense amplifier, the first transistor to receive a first control signal that changes between first and second voltage levels, the first voltage level corresponding to reverse-biasing gate-source of the first transistor, the second voltage level corresponding to forward-biasing gate-source of the first transistor;
a memory cell capacitor; and
a second transistor to receive a second control signal that changes between the first voltage level and a third voltage level, and the second transistor coupled between the memory cell capacitor and the first bit line,
wherein the third voltage level is different from the second voltage level.
2. The device as claimed in claim 1 , wherein the third voltage level is greater than the second voltage level.
3. The device as claimed in claim 2 , wherein the first transistor is of an N-channel type.
4. The device as claimed in claim 1 , wherein the third voltage level is lower than the second voltage level.
5. The device as claimed in claim 4 , wherein the first transistor is of a P-channel type.
6. The device as claimed in claim 1 , wherein the amplifier circuit comprises a third transistor that includes a first source-drain pass coupled to the first bit line at one end thereof and a first control electrode coupled to the second bit line, and a fourth transistor that includes a second source-drain pass coupled to the second bit line at one end thereof and a second control electrode coupled to the first bit line, and wherein the first, third and fourth transistors are substantially equal in threshold voltage to each other.
7. The device as claimed in claim 1 , further comprising:
first and second input output lines;
a third transistor coupled between the first bit line and the first input output line; and
a fourth transistor coupled between the second bit line and the second input output line; and
wherein the amplifier circuit comprises a fifth transistor that includes a first source-drain pass coupled to the first bit line at one end thereof and a first control electrode coupled to the second bit line, and a sixth transistor that includes a second source-drain pass coupled to the second bit line at one end thereof and a second control electrode coupled to the first bit line, and each of the fifth and sixth transistors is smaller in threshold voltage than each of the first and third transistors.
8. The device as claimed in claim 7 , wherein the fifth and sixth transistors are substantially equal in threshold voltage to each other.
9. The device as claimed in claim 7 , further comprising a seventh transistor coupled to the amplifier circuit to serve as the sense amplifier, and wherein the first transistor includes a third source-drain pass coupled to the other end of the first source-drain pass of the fifth transistor, and the seventh transistor includes a fourth source-drain pass coupled to the other end of the second source-drain pass of the sixth transistor.
10. A device comprising:
first and second bit lines;
an amplifier circuit coupled to the first and second bit lines;
a first transistor coupled to the amplifier circuit and cooperating with the amplifier circuit to serve as a sense amplifier, the first transistor to receive a first control signal that changes between first and second voltage levels, the first voltage level corresponding to reverse-biasing gate-source of the first transistor, the second voltage level corresponding to forward-biasing gate-source of the first transistor;
a memory cell capacitor; and
a second transistor to receive a second control signal that changes between the second voltage level and a third voltage level which is different from the first voltage level, and the second transistor coupled between the memory cell capacitor and the first bit line.
11. The device as claimed in claim 10 , wherein the third voltage level is greater than the second voltage level.
12. The device as claimed in claim 11 , wherein the first transistor is of an N-channel type.
13. The device as claimed in claim 10 , wherein the third voltage level is lower than the second voltage level.
14. The device as claimed in claim 13 , wherein the first transistor is of a P-channel type.
15. The device as claimed in claim 10 , wherein the amplifier circuit comprises a third transistor that includes a first source-drain pass coupled to the first bit line at one end thereof and a first control electrode coupled to the second bit line, and a fourth transistor that includes a second source-drain pass coupled to the second bit line at one end thereof and a second control electrode coupled to the first bit line, and wherein the first, third and fourth transistors are substantially equal in threshold voltage to each other.
16. The device as claimed in claim 10 , further comprising:
first and second input output lines;
a third transistor coupled between the first bit line and the first input output line; and
a fourth transistor coupled between the second bit line and the second input output line; and
wherein the amplifier circuit comprises a fifth transistor that includes a first source-drain pass coupled to the first bit line at one end thereof and a first control electrode coupled to the second bit line, and a sixth transistor that includes a second source-drain pass coupled to the second bit line at one end thereof and a second control electrode coupled to the first bit line, and each of the fifth and sixth transistors is smaller in threshold voltage than each of the first and third transistors.
17. The device as claimed in claim 16 , wherein the fifth and sixth transistors are substantially equal in threshold voltage to each other.
18. The device as claimed in claim 16 , further comprising a seventh transistor coupled to the amplifier circuit to serve as the sense amplifier, and wherein the first transistor includes a third source-drain pass coupled to the other end of the first source-drain pass of the fifth transistor, and the seventh transistor includes a fourth source-drain pass coupled to the other end of the second source-drain pass of the sixth transistor.
19. A method comprising:
amplifying, by a sense amplifier, a signal on a bit line which is coupled to a memory cell capacitor through a first transistor;
providing a second transistor included in the sense amplifier with a first control signal that changes between first and second voltage levels, the first voltage level corresponding to reverse-biasing gate-source of the second transistor, the second voltage level corresponding to forward-biasing gate-source of the second transistor; and
providing the first transistor with a second control signal that changes between third and fourth voltage levels, the third voltage level coinciding with one of the first and second voltage levels and the fourth voltage level being different from the other of the first and second voltage levels.