Method and electronic device for a simplified integration of high precision thinfilm resistors
View Patent ↗The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR.
1. An integrated circuit device, comprising:
a first metal interconnect layer, METn−1;
a first insulating layer over METn−1
a resistive layer of a thin film resistor (TFR) embedded within the first insulating layer;
a second metal interconnect layer, METn, over the first insulating layer such that the resistive layer of the TFR is between METn−1 and METn, wherein METn has a slot without conductive layer located over a portion of the resistive layer of the TFR;
a second insulating layer over METn;
a third metal interconnect layer METn+1 over the second insulating layer;
a first VIA extending through the second insulating layer, the slot, and the first insulting layer to connect METn+1 to the resistive layer of the TFR; and
a second VIA extending through the second insulating layer to connect METn+1 to METn.
2. The device of claim 1 , wherein a first portion of the first VIA extends through the second insulating layer and is wider than a second portion of the first VIA that extends through the slot and the first insulating layer.
3. The device of claim 1 , wherein the slot is wider than a width of the resistive layer of the TFR.
4. The device of claim 1 , wherein the first VIA physically contacts a conductive portion of METn+1, a conductive portion of METn, and the resistive layer of the TFR.