Injection-locked oscillator apparatus and method

1. An apparatus comprising:

a ring oscillator comprising a plurality of delay cells connected in cascade;

a main injection apparatus comprising a plurality of main buffers, wherein the main buffers receive a reference clock from their inputs and outputs of the main buffers are coupled to respective inputs of the delay cells; and

a replica injection apparatus comprising a plurality of replica buffers, wherein:

the replica buffers receive the reference clock from their inputs; and

the replica buffers are configured such that:

the replica buffers are tri-stated and each output is connected to ground when the ring oscillator operates in an injection-locked mode; and

each output is connected to ground through a capacitor when the ring oscillator operates in a calibration mode.

2. The apparatus of claim 1 , wherein:

the ring oscillator comprises a first delay cell, a second delay cell, a third delay cell and a fourth delay cell connected in cascade, and wherein an output of the fourth delay cell is connected to an input of the first delay cell.

3. The apparatus of claim 2 , wherein:

the main injection apparatus comprises a first main buffer, a second main buffer, a third main buffer and a fourth main buffer, and wherein:

an output of the first main buffer is connected to an input of the first delay cell;

an output of the second main buffer is connected to an input of the second delay cell;

an output of the third main buffer is connected to an input of the third delay cell; and

an output of the fourth main buffer is connected to an input of the fourth delay cell.

4. The apparatus of claim 3 , wherein:

the first main buffer is of a first gain;

the second main buffer is of a second gain;

the third main buffer is of a third gain equal to one half of the second gain; and

the fourth main buffer is turned off.

5. The apparatus of claim 4 , further comprising:

the replica injection apparatus comprises a first replica buffer, a second replica buffer and a third replica buffer, and wherein:

the first replica buffer is of a gain equal to the first gain of the first main buffer;

the second replica buffer is of a gain equal to the second gain of the second main buffer; and

the third replica buffer is of a gain equal to the third gain of the third main buffer.

6. The apparatus of claim 5 , further comprising:

an adjustable current source coupled to the delays cells, the main buffers and the replica buffers, wherein the adjustable current source provides bias currents for the delays cells, the main buffers and the replica buffers.

7. The apparatus of claim 6 , wherein:

the bias currents are adjusted such that a frequency of an output of the ring oscillator is approximately equal to a frequency of the reference clock.

8. A system comprising:

a calibration apparatus comprising an amplitude comparator, a frequency detector and a calibration state machine, wherein the calibration apparatus generates a fine-tuning code and a coarse-tuning code;

an adjustable current source coupled to the calibration apparatus; and

an injection-locked oscillator comprising:

a ring oscillator comprising a plurality of delay cells connected in cascade, wherein an output of the ring oscillator is connected to the calibration apparatus;

a main injection apparatus comprising a plurality of main buffers, wherein the main buffers receive a reference clock from their inputs and the outputs of the main buffers are coupled to respective inputs of the delay cells; and

a replica injection apparatus comprising a plurality of replica buffers, wherein bias currents of the delay cells, the main buffers and the replica buffers are provided by the adjustable current source.

9. The system of claim 8 , wherein:

the replica buffers receive the reference clock from their inputs; and

the replica buffers are configured such that:

the replica buffers are tri-stated and each output is connected to ground when the injection-locked oscillator operates in an injection-locked mode; and

each output is connected to ground through a capacitor when the injection-locked oscillator operates in a calibration mode.

10. The system of claim 8 , wherein:

the amplitude comparator has a first input receiving a reference signal and a second input receiving a clock signal from the output of the ring oscillator;

the frequency detector has a first input receiving the clock signal from the output of the ring oscillator and a second input receiving the reference clock; and

the calibration state machine has a first input coupled to an output of the amplitude comparator and a second input coupled to an output of the frequency detector.

11. The system of claim 10 , wherein:

the calibration state machine generates a fine-tuning calibration code and a coarse-tuning calibration code, and wherein:

the fine-tuning code is configured to adjust bias currents of the delay cells, the main buffers and the replica buffers; and

the coarse-tuning code is configured to adjust gains of the replica buffers and the main buffers.

12. The system of claim 11 , wherein:

the ring oscillator comprises:

a first delay cell, a second delay cell, a third delay cell and a fourth delay cell connected in series;

the main injection apparatus comprises a first main buffer, a second main buffer, a third main buffer and a fourth main buffer, and wherein:

an output of the first main buffer is connected to an input of the first delay cell;

an output of the second main buffer is connected to an input of the second delay cell;

an output of the third main buffer is connected to an input of the third delay cell; and

an output of the fourth main buffer is connected to an input of the fourth delay cell; and

the replica injection apparatus comprises a first replica buffer, a second replica buffer and a third replica buffer, and wherein the first replica buffer, the second replica buffer and the third replica buffer have inputs coupled to the reference clock.

13. The system of claim 12 , wherein:

the first replica buffer is of a gain equal to a first gain of the first main buffer;

the second replica buffer is of a gain equal to a second gain of the second main buffer; and

the third replica buffer is of a gain equal to a third gain of the third main buffer.

14. A method comprising:

during an injection-locked mode, coupling outputs of a plurality of replica buffers of a replica injection apparatus to ground, disabling the replica buffers and injecting a reference clock into a ring oscillator having a plurality of delay cells through a plurality of main buffers of a main injection apparatus, wherein:

the main buffers receive the reference clock from their inputs and the outputs of the main buffers are coupled to respective inputs of the delay cells; and

during a calibration mode, coupling each output of the plurality of replica buffers of the replica injection apparatus to ground through a capacitor and disabling the main buffers of the main injection apparatus; and

during the calibration mode, comparing an output signal of the ring oscillator with the reference clock and generating a fine-tuning calibration code and a coarse-tuning calibration code.

15. The method of claim 14 , further comprising:

comparing a frequency of the output signal of the ring oscillator with a frequency of the reference clock;

generating the fine-tuning calibration code based upon a first mismatch between the frequency of the output signal of the ring oscillator and the frequency of the reference clock; and

adjusting bias currents of the delay cells, the main buffers and the replica buffers based upon the fine-tuning calibration code.

16. The method of claim 15 , further comprising:

comparing an amplitude of the output signal of the ring oscillator with a predetermined reference level;

generating the coarse-tuning calibration code based upon a second mismatch between the amplitude of the output signal of the ring oscillator and the predetermined reference level; and

adjusting gains of the main buffers and the replica buffers based upon the coarse-tuning calibration code.

17. The method of claim 16 , further comprising:

digitally controlling the gains and the bias currents so as to minimize the first mismatch and the second mismatch over temperature and voltage variations.

18. The method of claim 17 , further comprising:

digitally controlling the gains of the replica buffers so as to match gains of their respective main buffers.

19. The method of claim 17 , further comprising:

adjusting the gains of the replica buffers and the main buffers until the amplitude of the output signal of the ring oscillator is greater than or equal to the predetermined reference level.

20. The method of claim 14 , wherein:

the capacitor is of a capacitance value approximately equal to a loading capacitance at an output of the main buffer.