Low power content-addressable memory
View Patent ↗A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. Further, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.
1. A content-addressable memory (CAM) comprising:
a plurality of bit cells in a stacked architecture, each of said plurality of bit cells including:
a pair of stacked storage elements situated in a first column;
a compare circuit coupled to said pair of stacked storage elements and a matchline of said CAM, said compare circuit situated in a second column;
said pair of stacked storage elements sharing bit lines.
2. The CAM of claim 1 , wherein said first column adjoins said second column.
3. The CAM of claim 1 , wherein said compare circuit is implemented using a plurality of transistors of a same conductivity type.
4. The CAM of claim 1 , wherein said compare circuit comprises a plurality of transistors arranged in pulldown-stack configurations coupled to said matchline.
5. The CAM of claim 1 , wherein said compare circuit is further configured to compare data stored in one of said pair of stacked storage elements against compare-data supplied by compare lines of said CAM and then apply a match or mismatch state to said matchline.
6. The CAM of claim 1 , wherein said compare circuit is further configured to compare compare-data supplied by compare lines of said CAM against data stored in one of said pair of stacked storage elements while concurrently applying a match or mismatch state to said matchline.
7. A content-addressable memory (CAM) comprising:
a plurality of bit cells in a stacked architecture, each of said plurality of bit cells including:
a pair of stacked storage elements situated in a first column;
a compare circuit coupled to said pair of stacked storage elements and a matchline of said CAM, said compare circuit situated in a second column;
said pair of stacked storage elements being coupled to separate bit lines.
8. The CAM of claim 7 , wherein said first column adjoins said second column.
9. The CAM of claim 7 , wherein said compare circuit is implemented using a plurality of transistors of a same conductivity type.
10. The CAM of claim 7 , wherein said compare circuit comprises a plurality of transistors arranged in pulldown-stack configurations coupled to said matchline.
11. The CAM of claim 7 , wherein said compare circuit is further configured to compare data stored in one of said pair of stacked storage elements against compare-data supplied by compare lines of said CAM and then apply a match or mismatch state to said matchline.
12. The CAM of claim 7 , wherein said compare circuit is further configured to compare compare-data supplied by compare lines of said CAM against data stored in one of said pair of stacked storage elements while concurrently applying a match or mismatch state to said matchline.
13. A content-addressable memory (CAM) bit cell comprising:
a pair of stacked storage elements situated in a first column;
a compare circuit coupled to said pair of stacked storage elements and configured to couple to a matchline, said compare circuit situated in a second column, and wherein said compare circuit comprises a plurality of transistors of a same conductivity type;
said pair of stacked storage elements sharing bit lines.
14. The CAM bit cell of claim 13 , wherein said first column adjoins said second column.
15. The CAM bit cell of claim 13 , wherein said compare circuit is implemented using a plurality of transistors of a same conductivity type.
16. The CAM bit cell of claim 13 , wherein said compare circuit is further configured to couple to compare lines through compare circuit transistors.
17. The CAM bit cell of claim 13 , wherein said compare circuit comprises a plurality of transistors arranged in pulldown-stack configurations coupled to said matchline.
18. The CAM bit cell of claim 13 , wherein said compare circuit is further configured to compare data stored in one of said pair of stacked storage elements against compare-data supplied by compare lines and then apply a match or mismatch state to said matchline.
19. The CAM bit cell of claim 13 , wherein said compare circuit is further configured to compare compare-data supplied by compare lines against data stored in one of said pair of stacked storage elements while concurrently applying a match or mismatch state to said matchline.