IP Library Granted Patent US 9,058,453
Granted Patent B2
US 9,058,453 · App. 13/902,701 · Granted Jun 16, 2015

System and method for configuring a channel

Inventors: Stephen William Keckler (San Jose, CA); William J. Dally (Los Altos Hills, CA); Steven Lee Scott (Eau Claire, WI); Brucek Kurdo Khailany (Austin, TX); Michael Allen Parker (San Jose, CA)
Assignee: NVIDIA Corporation
G06F17/5054
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,058,453
App. No.
13/902,701
Granted
Jun 16, 2015
Kind
B2
Abstract

A system and method are provided for configuring a plurality of pin resources. The method includes identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device and configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, where the first interface provides a first communication path between the primary ASIC device and a first device, and the second interface provides a second communication path between the primary ASIC device and a second device.

Claims (33)

1. A method, comprising:

identifying a plurality of pin resources of a primary application specific integrated circuit (ASIC) device; and

configuring the plurality of pin resources based on a pin distribution between a first interface and a second interface, wherein the first interface provides a first communication path between the primary ASIC device and a first device and the second interface provides a second communication path between the primary ASIC device and a second device.

2. The method of claim 1 , wherein the first device is a non-volatile storage device and the first communication path is between the storage device and a memory controller circuit within the primary ASIC device.

3. The method of claim 1 , wherein the first device is a memory device and the first communication path is between the memory device and a memory controller circuit within the primary ASIC device.

4. The method of claim 3 , wherein the first device includes expansion circuitry that is coupled between the first communication path and one or more memory devices.

5. The method of claim 1 , wherein the first device is a memory controller device and the first communication path is between the memory controller device and a network-on-chip circuit that is included within the primary ASIC device.

6. The method of claim 1 , wherein the second device is a router device and the second communication path is between the router device and a network interface controller circuit within the primary ASIC device.

7. The method of claim 1 , wherein the second device is a network interface controller device and the second communication path is between the network interface controller device and a network-on-chip circuit that is included within the primary ASIC device.

8. The method of claim 1 , wherein the configuring of the pin resources comprises:

enabling a first transmitter circuit of two transmitter circuits to provide a first signal to a first pad within the plurality of pin resources to transmit the first signal from the primary ASIC device to the first device on the first communication path; and

activating a path between the first pad and a first receiver circuit of two receiver circuits to receive a second signal transmitted from the first device to the primary ASIC device on the first communication path.

9. The method of claim 1 , wherein the configuring of the pin resources comprises:

selecting a first signal of the first interface for input to a transmitter circuit that is coupled to a first within the plurality of pin resources to transmit the first signal from the primary ASIC device to the first device on the first communication path; and

receiving a second signal transmitted from the first device to the primary ASIC device on the first communication path at an input to a receiver circuit within the primary ASIC device that is coupled to the first interface and the second interface.

10. The method of claim 1 , wherein the first communication path is a channel configured to provide one or more bi-directional paths between the primary ASIC device and the first device.

11. The method of claim 1 , further comprising:

determining that the pin distribution has changed; and

reconfiguring the plurality of pin resources based on the changed pin distribution.

12. The method of claim 11 , wherein the reconfiguring of the plurality of pin resources comprises:

splitting the plurality of pin resources into a first subset of pin resources and a second subset of pin resources;

configuring the first subset of pin resources to provide at least a portion of the first communication path; and

configuring the second subset of pin resources to provide at least a portion of the second communication path.

13. The method of claim 1 , wherein the configuring of the plurality of pin resources comprises:

coupling a first quantity of channels provided by the plurality of pin resources to a memory controller circuit within the primary ASIC device; and

coupling a second quantity of channels provided by the plurality of pin resources to a network interface controller circuit within the primary ASIC device, wherein a distribution of the channels specified by the first quantity and the second quantity equals the pin distribution.

14. A system, comprising:

a first device;

a second device; and

a primary application specific integrated circuit (ASIC) device comprising a plurality of pin resources, wherein the plurality of pin resources is configured based on a pin distribution between a first interface that provides a first communication path between the primary ASIC device and the first device and a second interface that provides a second communication path between the primary ASIC device and the second device.

15. The system of claim 14 , wherein the first device is a non-volatile storage device and the first communication path is between the storage device and a memory controller circuit within the primary ASIC device.

16. The system of claim 14 , wherein the first device is a memory device and the first communication path is between the memory device and a memory controller circuit within the primary ASIC device.

17. The system of claim 14 , wherein the first device is a memory controller device and the first communication path is between the memory controller device and a network-on-chip circuit that is included within the primary ASIC device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2013
From: KECKLER, STEPHEN WILLIAM; DALLY, WILLIAM J.; SCOTT, STEVEN LEE; KHAILANY, BRUCEK KURDO; PARKER, MICHAEL ALLEN
To: NVIDIA CORPORATION
Reel/Frame 031492/0598 →
Continuity (1)
Related Publication 20140351780A1 · Nov 27, 2014