IP Library Granted Patent US 9,134,776
Granted Patent B2
US 9,134,776 · App. 13/902,868 · Granted Sep 15, 2015

Device in computer system

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Quick Facts
Patent No.
US 9,134,776
App. No.
13/902,868
Granted
Sep 15, 2015
Kind
B2
Abstract

A device includes a PCH including a reset control pin and a disable control pin. A BIOS chip to control the PCH to send a low logic level from the reset control pin to the reset pin to reset a Ethernet controller. A timing adjusting circuit and the Ethernet controller. The Ethernet controller includes a reset pin and a disable pin, the reset pin is connected to the reset control pin via the timing adjusting circuit, and the disable pin is connected to the disable control pin via the timing adjusting circuit. The PCH sends a low logic level from the disable control pin to the disable pin to disable the Ethernet controller, and the timing adjusting circuit delays the low logic level, which makes the low logic level of the disable pin come later than the high logic level of the reset pin.

Claims (9)

1. A device comprising:

a platform controller hub PCH comprising a reset control pin and a disable control pin;

a basic input/output system BIOS chip, connected to the PCH, to control the PCH to send a low logic level from the reset control pin to the reset pin to reset a Ethernet controller during booting of the device;

a timing adjusting circuit; and

the Ethernet controller, comprising a reset pin and a disable pin, the reset pin connected to the reset control pin via the timing adjusting circuit, and the disable pin connected to the disable control pin via the timing adjusting circuit;

wherein the PCH is further controlled to send a low logic level from the disable control pin to the disable pin to disable the Ethernet controller during booting of the device, and the timing adjusting circuit is configured to delay the low logic level, which makes the low logic level of the disable pin come later than the high logic level of the reset pin.

2. The device according to claim 1 , wherein the timing adjusting circuit is a programmable component.

3. The device according to claim 2 , wherein the timing adjusting circuit is a EPM3032ATC44-10N.

4. The device according to claim 1 , wherein the Ethernet controller is a 82599 chip.

Assignments (3)
CHANGE OF NAME Recorded Mar 10, 2022
From: HONGFUJIN PRECISION ELECTRONICS(TIANJIN)CO.,LTD.
To: FULIAN PRECISION ELECTRONICS (TIANJIN) CO., LTD.
Reel/Frame 059620/0142 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2018
From: HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD.; HON HAI PRECISION INDUSTRY CO., LTD.
To: HONGFUJIN PRECISION ELECTRONICS(TIANJIN)CO.,LTD.
Reel/Frame 045501/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2013
From: WU, KANG; TIAN, BO
To: HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD.; HON HAI PRECISION INDUSTRY CO., LTD.
Reel/Frame 030488/0220 →