Electric signal conversion
View Patent ↗In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.
1. An electrical signal converter, comprising:
a plurality of inputs for receiving a first species of signal;
a plurality of n, converter elements for converting the first species of signal into a second species of signal, wherein n>3;
a switch for mapping the plurality of inputs to the plurality of converter elements; and
logic configured to cause the switch to map the inputs on a plurality of successive input cycles to different converter elements according to a delta-two-maximum pattern, wherein on a first input cycle, a converter element is used at position k, and on a second conversion cycle the converter element is used at position k t+1 , wherein |k−k t+1 |≦2.
2. The electrical signal converter of claim 1 , wherein the converter elements are digital-to-analog converter elements.
3. The electrical signal converter of claim 2 , wherein the plurality of inputs form a thermometer code.
4. The electrical signal converter of claim 1 , wherein the converter elements are analog-to-digital converters.
5. The electrical signal converter of claim 4 , wherein the second species of signal comprises a thermometer code.
6. The electrical signal converter of claim 1 , wherein the logic is configured to select the delta-two-maximum pattern according to a pseudorandom input.
7. The electrical signal converter of claim 1 , wherein the logic is configured to select the delta-two-maximum pattern according to a pseudorandom input plus a constant.
8. The electrical signal converter of claim 1 , wherein the pattern encompasses n ordered converter elements and wherein the delta-two-maximum pattern comprises:
if k is even, k t+1 =k+2; and if k is odd, k t+1 =k−2.
9. The electrical signal converter of claim 8 , wherein the delta-two-maximum pattern further comprises:
if k==1, k t+1 =2; and if k is even and k==n, k t+1 =k−1.
10. The electrical signal converter of claim 1 , wherein the pattern encompasses n ordered converter elements and wherein the delta-two-maximum pattern comprises swapping k and k+1.
11. The electrical signal converter of claim 10 , wherein the delta-two-maximum pattern further comprises:
on even cycles, if k is odd and k≠n, swap k and k+1;
on odd cycles, if k is even and k≠n, swap k and k+1.
12. A delta-sigma modulator comprising:
an analog-to-digital converter configured to receive an analog input and provide a digital output, the analog-to-digital converter comprising a plurality of n ordered converter elements, wherein n>3, and logic to rotate converter elements according to a first stepwise delta-two-maximum pattern;
a digital-to-analog converter configured to receive the digital output of the analog-to-digital converter and provide an analog output, the digital-to-analog converter comprising a plurality of ordered converter elements and logic rotate converter elements according to a second stepwise delta-two-maximum pattern;
a loop filter configured to receive the analog input and the analog output of the digital-to-analog converter, and to provide a filtered analog signal the analog-to-digital converter; and
element selection logic configured to select a number of steps;
wherein the first stepwise delta-two-maximum pattern and second stepwise delta-two-maximum pattern each ensure that a converter element used at a position k on a first conversion cycle is used at k t+1 on a second conversion cycle, wherein |k−k t+1 |≦2.
13. The delta-sigma modulator of claim 12 , wherein:
at least one of the delta-two-maximum patterns comprises, for element k, if k is of a first species, k t+1 =k+2; if k is of a second species, k t+1 =k−2.
14. The delta-sigma modulator of claim 12 , wherein:
the digital-to-analog converter comprises n converter elements;
the delta-two-maximum pattern comprises two cycles, wherein, for element k:
on the first cycle, if k is odd, swap k and k+1;
on the second cycle, if k is even, swap k and k+1.
15. The delta-sigma modulator of claim 12 , wherein the element selection logic selects the number of steps by calculating a pseudorandom number plus a constant.
16. A method performed by an electrical signal converter, comprising:
during a first time period, selecting a first converter element from among a plurality of n available ordered converter elements in the electrical signal converter, wherein n>3;
during a second time period:
calculating a pseudorandom number;
selecting a second converter element by stepping through available converter elements according to a delta-two-maximum pattern, the number of steps being a function of the pseudorandom number and being less than two.
17. The method of claim 16 , wherein the function of the pseudorandom number includes addition of a constant.
18. The method of claim 17 , wherein the constant is one.
19. The method of claim 16 , wherein the delta-two-maximum pattern includes the steps 1-2-4-6-8 and 7-5-3-1.
20. The method of claim 16 , wherein the delta-two-maximum pattern comprises shifting converter elements up or down two elements
21. The method of claim 16 , wherein the delta-two-maximum pattern comprises swapping adjacent converter elements.
22. The method of claim 16 , wherein the delta-two-maximum pattern comprises:
for element k, if k is of a first species, k t+1 =k+2; if k is of a second species, select k t+1 =k−2.
23. The method of claim 16 , wherein:
the delta-two-maximum pattern comprises two cycles, wherein, for element k:
on the first cycle, for a first species of k, swap k and k+1;
on the second cycle, for a second species of k, swap k and k+1.