Semiconductor device and method for manufacturing the same
View Patent ↗Embodiments relate to a method for manufacturing a semiconductor device including at least one of: (1) Forming a lower electrode pattern on a substrate. (2) Forming an etch stop film on/over the lower electrode pattern. (3) Forming a first interlayer insulating layer on/over the etch stop film. (4) Forming an upper electrode pattern on/over the first interlayer insulating layer. (5) Forming a second interlayer insulating layer on/over the upper electrode pattern. (6) Forming an etch blocking layer positioned between the lower electrode pattern and the upper electrode pattern which passes through the second interlayer insulating layer and the first interlayer insulating layer. (7) Forming a cavity which exposes a side of the etch blocking layer by etching the second interlayer insulating layer and the first interlayer insulating layer. (8) Forming a contact ball in the cavity.
1. A semiconductor device comprising:
a lower electrode pattern on or over a substrate;
an etch stop film over the lower electrode pattern and the substrate;
a first interlayer insulating layer over the etch stop film;
an upper electrode pattern over the first interlayer insulating layer;
a second interlayer insulating layer over the upper electrode pattern;
etch blocking layers between the lower electrode pattern and the upper electrode pattern, wherein the etch blocking layers pass through the second interlayer insulating layer and the first interlayer insulating layer, and the lower electrode pattern is between the etch blocking layers;
a cavity in the second interlayer insulating layer and the first interlayer insulating layer, wherein the cavity is configured to expose at least a portion of a side of the etch blocking layer; and
a contact ball in the cavity.
2. The semiconductor device of claim 1 , wherein the etch blocking layers overlap with a region of the etch stop film between the lower electrode pattern and the upper electrode pattern in a vertical direction.
3. The semiconductor device of claim 1 , wherein the etch blocking layers are in contact with a region of the etch stop film between the lower electrode pattern and the upper electrode pattern.
4. The semiconductor device of claim 1 , wherein the etch blocking layers are in contact with at least a portion of a side of the upper electrode pattern.
5. The semiconductor device of claim 1 , wherein:
the etch blocking layers are spaced apart from the upper electrode pattern; and
a portion of the second interlayer insulating layer is between the second etch blocking layer and the upper electrode pattern.
6. The semiconductor device as claimed in claim 5 , further comprising:
a contact connected to the upper electrode pattern and which passes through the second interlayer insulating layer; and
a connection line over the second interlayer insulating layer and which connects the contact to the etch blocking layers.
7. The semiconductor device of claim 1 , wherein the etch stop film comprises a material having a higher etch selectivity than the first interlayer insulating layer.
8. The semiconductor device of claim 7 , wherein the etch selectivity is for a dry etchant that etches the first and second interlayer insulating layers.
9. The semiconductor device of claim 1 , wherein the etch stop film comprises silicon nitride.
10. The semiconductor device of claim 9 , wherein the first interlayer insulating layer includes at least one of SiO 2 , Si x N y (where x and y are real numbers), a fluorosilicate glass, an undoped silicate glass, a borophosphosilicate glass, and tetraethoxysilane.
11. The semiconductor device of claim 1 , wherein the first interlayer insulating layer includes at least one of SiO 2 , Si x N y (where x, and y are real numbers), a fluorosilicate glass, an undoped silicate glass, a borophosphosilicate glass, and tetraethoxysilane.
12. The semiconductor device of claim 1 , wherein the etch blocking layers comprise a conductive material.
13. The semiconductor device of claim 12 , wherein the conductive material has a higher etch selectivity than the first and second interlayer insulating layers.
14. The semiconductor device of claim 13 , wherein the etch selectivity is for each of a dry etchant and a wet etchant that etch the first and second interlayer insulating layers.
15. The semiconductor device of claim 12 , wherein the conductive material comprises tungsten.
16. The semiconductor device of claim 15 , further comprising a barrier material between the etch blocking layers and the first and second interlayer insulating layers.
17. The semiconductor device of claim 16 , wherein the barrier material comprises a metal having a thickness of 50 Å to about 200 Å.
18. The semiconductor device of claim 16 , wherein the barrier material comprises TiN, Ti, or TiN/Ti.
19. The semiconductor device of claim 1 , wherein the etch blocking layers fill trenches on opposed sides of the lower electrode pattern, wherein each trench is between the lower electrode pattern and an adjacent electrode of the upper electrode pattern.
20. The semiconductor device of claim 19 , wherein the trenches expose a portion of the upper electrode pattern.