Time-interleaved analog-to-digital converter bandwidth matching

1. A time-interleaved Analog-to-Digital Converter (ADC) comprising:

a number of sub-ADC circuits;

wherein each said sub-ADC comprises a sample-and-hold circuit;

wherein each said sample-and-hold circuit comprises:

a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of said switch, said switch for switching between a sample mode and a hold mode; and

wherein said bootstrap circuit is used to further adjust said constant voltage level between said input terminal and said gate terminal of said switch to adjust an ON state of an intrinsic resistance of said switch.

2. The time-interleaved ADC of claim 1 , wherein each said sub-ADC samples an input signal at a lower sampling rate with respect to an overall sampling rate of said time-interleaved ADC.

3. The time-interleaved ADC of claim 1 , further comprising a capacitor bank associated with said bootstrap circuit such that a setting of said capacitor bank affects said ON state of said intrinsic resistance of said switch by affecting said constant voltage level.

4. The time-interleaved ADC of claim 3 , wherein said capacitor bank is connected between a control signal and ground, said control signal being between said bootstrap circuit and a gate terminal.

5. The time-interleaved ADC of claim 3 , wherein said capacitor bank is connected in parallel to a main capacitor of said bootstrap circuit.

6. The time-interleaved ADC of claim 3 , wherein said capacitor bank comprises a binary weighted capacitor bank.

7. The time-interleaved ADC of claim 3 , further comprising a memory coupled to said capacitor bank, said memory configured to store a setting of said capacitor bank.

8. The time-interleaved ADC of claim 7 , wherein said memory comprises a one-time programmable memory.

9. A method for matching bandwidths within a time-interleaved Analog-to-Digital Converter (ADC), the method comprising:

determining a frequency response of a sample-and-hold circuit for each of a set of sub-ADC circuits within a time-interleaved ADC; and

adjusting a bandwidth of at least one of said sub-ADC circuits by adjusting an intrinsic resistance of an ON state of a switch associated with a sample-and-hold circuit of said at least one of said sub-ADC circuits, said adjusting causing bandwidths among said sub-ADC circuits to be more closely matched.

10. The method of claim 9 , wherein adjusting said intrinsic resistance of said ON state comprises adjusting a capacitive trim load on a gate terminal of said switch.

11. The method of claim 10 , wherein said capacitive trim load is placed in parallel to a main bootstrap capacitor of a sample-and-hold circuit of at least one of sub-ADC circuits to increase a bandwidth of said at least one sub-ADC circuit.

12. The method of claim 10 , wherein said capacitive trim load is placed between said gate terminal of said switch of a sample-and-hold circuit of at least one of sub-ADC circuits and ground to increase a bandwidth of said at least one sub-ADC circuit.

13. The method of claim 10 , wherein said capacitive trim load comprises a capacitor bank.

14. The method of claim 13 , further comprising, storing a setting of said capacitor bank setting into a memory associated with said capacitor bank.

15. The method of claim 9 , further comprising, increasing a bandwidth of each of said sub-ADC circuits to match a bandwidth of a sub-ADC circuit within said time-interleaved ADC having the highest bandwidth.

16. The method of claim 9 , further comprising, decreasing a bandwidth of each of said sub-ADC circuits to match a bandwidth of a sub-ADC circuit within said time-interleaved ADC having the smallest bandwidth.