IP Library Granted Patent US 9,391,870
Granted Patent B2
US 9,391,870 · App. 13/908,108 · Granted Jul 12, 2016

Method and system for symmetric transmit and receive latencies in an energy efficient PHY

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Quick Facts
Patent No.
US 9,391,870
App. No.
13/908,108
Granted
Jul 12, 2016
Kind
B2
Abstract

Aspects of a method and system for symmetric transmit and receive latencies in an energy efficient PHY are provided. In this regard, a delay introduced by a PHY of a network device for outbound traffic and a delay introduced by the PHY for inbound traffic may be controlled such that a transmit delay of the network device is equal, within a tolerance, to a receive latency of the network device. The delays may be controlled based on whether one or more energy efficiency features are enabled in the PHY. The delay introduced by the PHY for outbound traffic may be controlled based on an amount of buffered inbound traffic. The delay introduced by the PHY for inbound traffic may be controlled based on an amount of buffered outbound traffic. The delays may be controlled such that said receive latency and the transmit latency are approximately constant regardless of a mode of operation of the network device.

Claims (35)

1. A method, comprising:

determining, by a network device comprising one or more circuits, a difference between a first amount of latency in a first path within a physical layer device of the network device in a first direction and a second amount of latency in a second path within the physical layer device in a second direction; and

adjusting, by the network device, an amount of delay in the first path within the physical layer device in the first direction using the determined difference,

wherein the adjusting the amount of delay comprises controlling one or more buffers of the network device.

2. The method of claim 1 , wherein the first path is a transmit path and the second path is a receive path.

3. The method of claim 1 , wherein the first path is a receive path and the second path is a transmit path.

4. The method of claim 1 , wherein the adjusting the amount of delay further comprises at least one of controlling a size of the one or more buffers, controlling one or more thresholds of the one or more buffers, or controlling a rate at which data is read out of the one or more buffers.

5. The method of claim 1 , wherein the adjusting the amount of delay further comprises controlling a delay introduced by the physical layer device for outbound traffic using an amount of buffered inbound traffic.

6. The method of claim 1 , wherein the adjusting the amount of delay further comprises controlling a delay introduced by the physical layer device for inbound traffic using an amount of buffered outbound traffic.

7. The method of claim 1 , wherein the adjusting the amount of delay further comprises controlling a delay using a type of traffic.

8. The method of claim 1 , wherein the adjusting the amount of delay further comprises controlling a delay using traffic patterns.

9. The method of claim 1 , wherein the adjusting the amount of delay further comprises adjusting the amount of delay in the first path within the physical layer device such that the first amount of latency in the first path within the physical layer device is substantially equal to the second amount of latency in the second path within the physical layer device.

10. A network device, comprising:

one or more circuits, one or more processors, or any combination thereof configured to:

determine a difference between a first amount of latency in a first path within a physical layer device of the network device in a first direction and a second amount of latency in a second path within the physical layer device in a second direction; and

adjust, based on an energy efficiency control policy that controls energy efficient network features of the physical layer device, an amount of delay in the first path within the physical layer device in the first direction using the determined difference,

wherein the adjusting the amount of delay comprises controlling one or more buffers of the network device.

11. The network device of claim 10 , wherein the first path is a transmit path and the second path is a receive path.

12. The network device of claim 10 , wherein the first path is a receive path and the second path is a transmit path.

13. The network device of claim 10 , wherein the energy efficiency control policy controls entry by the physical layer device into one of low power idle and sub-rating.

14. The network device of claim 10 , further comprising the one or more circuits, the one or more processors, or any combination thereof configured to control at least one of a size of the one or more buffers, one or more thresholds of the one or more buffers, or a rate at which data is read out of the one or more buffers.

15. The network device of claim 10 , further comprising the one or more circuits, the one or more processors, or any combination thereof configured to control a delay introduced by the physical layer device for outbound traffic using an amount of buffered inbound traffic.

16. The network device of claim 10 , further comprising the one or more circuits, the one or more processors, or any combination thereof configured to control a delay introduced by the physical layer device for inbound traffic using an amount of buffered outbound traffic.

17. The network device of claim 10 , further comprising the one or more circuits, the one or more processors, or any combination thereof configured to control a delay using a type of traffic.

18. The network device of claim 10 , further comprising the one or more circuits, the one or more processors, or any combination thereof configured to control a delay using traffic patterns.

19. The network device of claim 10 , further comprising the one or more circuits, the one or more processors, or any combination thereof configured to adjust the amount of delay in the first path within the physical layer device such that the first amount of latency in the first path within the physical layer device is substantially equal to the second amount of latency in the second path within the physical layer device.

20. A method performed by a network device, comprising:

determining a difference between a first amount of latency in a first path within a physical layer device in a first direction and a second amount of latency in a second path within the physical layer device in a second direction; and

adjusting, by an energy efficiency control policy module that controls energy efficient network features of the physical layer device of the network device, an amount of delay in the first path within the physical layer device in the first direction, the amount of delay being adjusted using the difference,

wherein the adjusting the amount of delay comprises at least one of:

controlling at least one of: a size of one or more buffers, one or more thresholds of the one or more buffers, or a rate at which data is read out of the one or more buffers;

controlling a delay introduced by the physical layer device for outbound traffic using an amount of buffered inbound traffic;

controlling a delay introduced by the physical layer device for inbound traffic using an amount of buffered outbound traffic;

controlling a delay using a type of traffic; or

controlling a delay using traffic patterns.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2013
From: DIAB, WAEL WILLIAM; POWELL, SCOTT
To: BROADCOM CORPORATION
Reel/Frame 030531/0465 →