Semiconductor device, control method for the semiconductor device and information processing system including the same
The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side.
1. A device comprising:
a first semiconductor chip that comprises:
a plurality of first terminals;
a plurality of second terminals;
a plurality of first memory blocks each including a plurality of first memory cells, each of the first memory blocks being configured to be accessed to produce first data;
a plurality of first circuits each producing a first output timing control signal;
a plurality of first buffers each coupled to an associated one of the first terminals, an associated one of the first memory blocks and an associated one of the first circuits and configured to respond to the first output timing control signal produced from the associated one of the first circuits to drive the associated one of the first terminals in accordance with the first data produced from the associated one of the first memory blocks; and
a plurality of second buffers each coupled to an associated one of the second terminals and an associated one of the first circuits and configured to respond to the first output timing control signal produced from the associated one of the first circuits to drive the associated one of the second terminals;
a second semiconductor chip that comprises:
a plurality of first through-vias each penetrating the second semiconductor chip and having first and second ends;
a. plurality of second through-vias each penetrating the second semiconductor chip and having third and fourth ends;
a plurality of second memory blocks each including a plurality of second memory cells, each of the second memory blocks being configured to be accessed to produce second data;
a plurality of second circuits each producing a second output timing control signal;
a plurality of third buffers each coupled to an associated one of the first through-vias, an associated one of the second memory blocks and an associated one of the second circuits and configured to respond to the second output timing control signal produced from the associated one of the second circuits to drive the associated one of the first through-vias in accordance with the second data produced from an associated one of the second memory blocks; and
a plurality of fourth buffers each coupled to an associated one of the second through-vias and an associated one of the second circuits and configured to respond to the second output timing control signal produced from the associated one of the second circuits to drive the associated one of the second through-vias; and
a third semiconductor chip that comprises:
a plurality of third terminals; and
a plurality of fourth terminals;
wherein the first and second semiconductor chips are stacked with each other such that each of the first terminals is connected to the first end of an associated one of the first through vias and each of the second terminals is connected to the third end of an associated one of the second through-vias; and
wherein the third semiconductor chip is coupled to the second semiconductor chip such that each of the third terminals is electrically connected to the second end of an associated one of the first through-vias and each of the fourth terminals is electrically connected to the fourth end of an associated one of the second through-vias.
2. The device as claimed in claim 1 , wherein the third semiconductor chip is supplied at each of the third terminals with a data signal responsive to a selected one of the first and second data and at each of the fourth terminals with a timing signal responsive to a selected one of the first and second output timing control signals.
3. The device as claimed in claim 1 , wherein the first semiconductor chip further comprises a plurality of third through-vias each penetrating the first semiconductor chip and having fifth and sixth ends and a plurality of fourth through-vias each penetrating the first semiconductor chip and having seventh and eighth ends, each of the first terminals being provided on the fifth end of an associated one of the third through vias, and each of the second terminals being provided on the seventh ends of an associated one of the fourth through-vias.
4. The device as claimed in claim 1 , wherein each of the first through-vias is physically close to an associated one of the second through-vias.
5. The device as claimed in claim 3 , wherein each of the first through-vias is physically close to an associated one of the second through-vias and each of the third through-vias is physically close to an associated one of the fourth through-vias.
6. The device as claimed in claim 5 , wherein each of the first through-vias is vertically aligned with an associated one of the third through-vias, and each of the second through-vias is vertically aligned with an associated one of the fourth through-vias.
7. A device comprising:
a first semiconductor chip that comprises:
a plurality of first terminals;
a plurality of second terminals;
a plurality of first memory banks each including a plurality of first memory cells, each of the first memory banks being configured to produce first data read out from a selected one of the first memory cells;
a plurality of first buffers each configured to drive, when the first semiconductor chip selected, an associated one of the first terminals to produce a first data signal thereon in response to the first data; and
a plurality of second buffers each configured to drive, when the first semiconductor chip is selected, an associated one of the second terminals to assert a first control signal that indicates the first data signal on the associated one of the first terminals being valid; and
a second semiconductor chip that comprises:
a plurality of third terminals;
a plurality of fourth terminals;
a plurality of second memory banks each including a plurality of second memory cells, each of the second memory banks being configured to produce second data read out from a selected one of the second memory cells;
a plurality of third buffers each configured to drive, when the second semiconductor chip selected, an associated one of the third terminals to produce a second data signal thereon in response to the second data;
a plurality of fourth buffers each configured to drive, when the second semiconductor chip selected, an associated one of the fourth terminals to assert a second control signal that indicates the second data signal on the associated one of the third terminals being valid;
a plurality of first through-vias each penetrating the second semiconductor chip and including first and second ends, the first end of each of the first through-vias being connected to an associated one of the third terminals; and
a plurality of second through-vias each penetrating the second semiconductor chip and including third and fourth ends, the third end of each of the second through-vias being connected to an associated one of the fourth terminals; and
the first and second semiconductor chips being stacked with each other such that each of the first terminals is connected to the second end of an associated one of the first through-vias and each of the second terminals is connected to the fourth end of an associated one of the second through-vias.
8. The device as claimed in claim 7 , further comprising a third semiconductor chip that comprises a plurality of fifth terminals and a plurality of sixth terminals, each of the fifth terminals being electrically connected to an associated one of the third terminals, and each of the sixth terminals being electrically connected to an associated one of the fourth terminals.
9. The device as claimed in claim 8 , wherein:
when the first semiconductor chip is selected, the third semiconductor chip is supplied at at least one of the fifth terminals with the first data signal and at an associated one of the sixth terminals with the first control signal; and
when the second semiconductor chip is selected, the third semiconductor chip is supplied at at least one of the fifth terminals with the second data signal and at an associated one of the sixth terminals with the second control signal.
10. The device as claimed in claim 9 , wherein the first semiconductor chip further comprises a plurality of third through-vias each penetrating the first semiconductor chip and having fifth and sixth ends and a plurality of fourth through-vias each penetrating the first semiconductor chip and having seventh and eighth ends, each of the first terminals being provided on the fifth end of an associated one of the third through-vias, and each of the second terminals being provided on the seventh ends of an associated one of the fourth through-vias.
11. The device as claimed in claim 10 , wherein each of the first through-vias is physically close to an associated one of the second through-vias and each of the third through-vias is physically close to an associated one of the fourth through-vias.
12. The device as claimed in claim 11 , wherein each of the first through-vias is vertically aligned with an associated one of the third through-vias, and each of the second through-vias is vertically aligned with an associated one of the fourth through-vias.