Driver circuit with asymmetric boost
View Patent ↗A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node, the first circuit being configured to receive the signal and drive the signal on the output node at a first voltage. The circuit may also include a signal adjust circuit configured to adjust a current of the signal driven by the first circuit. The signal adjust circuit may be configured to apply a first current adjustment to adjust the current of the signal at one but not both of a falling edge of the signal or a rising edge of the signal.
1. A circuit comprising:
an input node configured to receive a signal;
an output node configured to be coupled to a load;
a first circuit coupled between the input node and the output node, the first circuit configured to receive the signal and drive the signal on the output node at a first voltage; and
a signal adjust circuit configured to adjust a current of the signal driven by the first circuit, the signal adjust circuit configured to apply a first current adjustment to adjust the current of the signal at one but not both of a falling edge of the signal or a rising edge of the signal.
2. The circuit of claim 1 , wherein when the signal adjust circuit is configured to apply the first current adjustment at the falling edge of the signal, the signal adjust circuit is further configured to apply a second current adjustment at the rising edge of the signal.
3. The circuit of claim 1 , wherein when the signal adjust circuit is configured to apply the first current adjustment to the signal at the rising edge of the signal, the signal adjust circuit is further configured to apply a second current adjustment to the signal at the falling edge of the signal.
4. The circuit of claim 1 , wherein the first current adjustment results in adding current to or subtracting current from the current of the signal at the output node.
5. The circuit of claim 1 , wherein the signal is differential and includes a positive signal and a negative signal, wherein the signal adjust circuit is further configured to apply the first current adjustment to the positive signal or to the negative signal.
6. The circuit of claim 1 , wherein an amount of current applied by the first current adjustment to the signal may be adjusted.
7. The circuit of claim 1 , wherein the signal adjust circuit is further configured to apply the first current adjustment to selected falling edges of the signal or selected rising edges of the signal.
8. The circuit of claim 1 , further comprising:
an active device coupled to the output node; and
a second circuit coupled to the input node and to the active device at an intermediate node, the second circuit configured to receive the signal and to drive the signal to the active device at a second voltage, wherein the signal adjust circuit is configured to apply the first current adjustment at the intermediate node.
9. The circuit of claim 8 , wherein the current in the signal adjust circuit is reduced compared to the adjustment to the current of the signal at the output node.
10. A circuit comprising:
an input node configured to receive a signal;
an output node configured to be coupled to a load;
a first circuit coupled between the input node and the output node, the first circuit configured to receive the signal and drive the signal on the output node at a first voltage; and
a signal adjust circuit configured to provide both additive boosting of the signal at the output node at one but not both of a rising edge of the signal or a falling edge of the signal and to provide subtractive boosting of the signal at the output node at one but not both of the rising edge of the signal or the falling edge of the signal.
11. The circuit of claim 10 , wherein the signal adjust circuit is configured to provide the additive boosting of the signal at one but not both of the rising edge of the signal or the falling edge of the signal during a first period and to provide the subtractive boosting of the signal at one but not both of the rising edge of the signal or the falling edge of the signal during a second period, wherein the first and second periods do not overlap.
12. The circuit of claim 10 , wherein the signal adjust circuit is further configured:
to provide the additive boosting of the signal at the rising edge of the signal and the subtractive boosting of the signal at the falling edge of the signal; or to provide the additive boosting of the signal at the falling edge of the signal and the subtractive boosting of the signal at the rising edge of the signal.
13. The circuit of claim 10 , wherein the signal adjust circuit is further configured to vary an amount of the additive boosting and the subtractive boosting.
14. The circuit of claim 10 , wherein the signal adjust circuit is further configured to apply additive or subtractive boosting to selected falling edges of the signal or to selected rising edges of the signal.
15. The circuit of claim 10 , wherein the signal is differential and includes a positive signal and a negative signal, wherein the signal adjust circuit is further configured to provide the additive boosting or the subtractive boosting to the positive signal or the negative signal.
16. The circuit of claim 10 , wherein the signal adjust circuit is further configured to provide the additive boosting of the signal at the output node at selected rising edges of the signal or at selected falling edges of the signal and to provide the subtractive boosting of the signal at the output node at the selected rising edge of the signal or at the selected falling edge of the signal.
17. A method of boosting a signal, the method comprising:
receiving a signal at an input node of a driver;
driving the signal on an output node of the driver at a first voltage, the output node configured to be coupled to a load;
providing additive boosting of the signal at the output node at one but not both of a rising edge of the signal or a falling edge of the signal; and
providing subtractive boosting of the signal at the output node at one but not both of the rising edge of the signal or the falling edge of the signal.
18. The method of claim 17 , wherein the providing the additive boosting of the signal at the output node at one but not both of the rising edge of the signal or the falling edge of the signal occurs during a first period and the providing the subtractive boosting of the signal at the output node at one but not both of the rising edge of the signal or the falling edge of the signal occurs during a second period, wherein the first and second periods do not overlap.
19. The method of claim 17 , wherein the additive boosting of the signal is provided at the rising edge of the signal and the subtractive boosting of the signal is provided at the falling edge of the signal or the additive boosting of the signal is provided at the falling edge of the signal and the subtractive boosting of the signal is provided at the rising edge of the signal.
20. The method of claim 17 , further comprising varying an amount of the additive boosting or the subtractive boosting.